ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 720

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1BA-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1BA-AUR
Manufacturer:
Atmel
Quantity:
10 000
33.8.2
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• USART_MODE
• USCLKS: Clock Selection
• CHRL: Character Length.
720
720
INVDATA
ONEBIT
Value
Value
Value
31
23
15
7
0xE
0xF
0x0
0x1
0x2
0x3
0x4
0x6
0x8
0
1
3
0
SAM3S Preliminary
SAM3S Preliminary
USART Mode Register
CHMODE
CHRL
VAR_SYNC
MODSYNC
HW_HANDSHAKING
30
22
14
US_MR
0x40024004 (0), 0x40028004 (1)
Read-write
6
Name
5_BIT
SPI_MASTER
IS07816_T_0
IS07816_T_1
SPI_SLAVE
NORMAL
MODEM
RS485
Name
Name
MCK
IRDA
SCK
DIV
DSNACK
MAN
Description
Character length is 5 bits
29
21
13
5
NBSTOP
USCLKS
Description
Normal mode
RS485
Hardware Handshaking
Modem
IS07816 Protocol: T = 0
IS07816 Protocol: T = 1
IrDA
SPI Master
SPI Slave
Description
Master Clock MCK is selected
Internal Clock Divided MCK/DIV (DIV=8) is selected
Serial Clock SLK is selected
FILTER
INACK
28
20
12
4
“USART Write Protect Mode Register” on page
OVER
27
19
11
3
CLKO
PAR
26
18
10
2
USART_MODE
MAX_ITERATION
MODE9
25
17
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
MSBF/CPOL
SYNC/CPHA
741.
24
16
8
0

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