ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 393

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.14 Asynchronous Page Mode
23.14.1
Figure 23-31. Page Mode Read Protocol (Address MSB and LSB are defined in
6500C–ATARM–8-Feb-11
Protocol and Timings in Page Mode
A[MSB]
A[LSB]
D[7:0]
MCK
NRD
NCS
The SMC supports asynchronous burst reads in page mode, providing that the page mode is
enabled in the SMC_MODE register (PMEN field). The page size must be configured in the
SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
enables the user to define different read timings for the first access within one page, and next
accesses within the page.
Table 23-5.
Note:
Figure 23-31
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1. “A” denotes the address bus of the memory device.
NCS_RD_PULSE
shows the NRD and NCS timings in page mode access.
Page Address and Data Address within a Page
tpa
Page Address
A[23:2]
A[23:3]
A[23:4]
A[23:5]
sa
) as shown in
(1)
NRD_PULSE
tsa
Table
Figure
23-5.
Table
23-31. When in page mode, the SMC
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
SAM3S Preliminary
NRD_PULSE
23-5)
pa
tsa
) takes longer than the subse-
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