ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 262

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Quantity
Price
Part Number:
ATSAM3S1BA-AU
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Part Number:
ATSAM3S1BA-AUR
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Quantity:
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262
Functional Description
SAM3S Preliminary
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in
the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock
divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow
Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of
the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup
Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must
either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must
reprogram it to meet the maximum Watchdog period the application requires.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset
resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode
parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer under-
flow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The
Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow
Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result,
writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur,
the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode
Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register
(WDT_SR).
To prevent a software deadlock that continuously triggers the Watchdog, the reload of the
Watchdog must occur while the Watchdog counter is within a window between 0 and WDD,
WDD is defined in the WatchDog Mode Register WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD
results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the
WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the
WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole
range [0; WDV] and does not generate an error. This is the default configuration on reset (the
WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an inter-
rupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset
controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset
controller programmer Datasheet. In that case, the processor and the Watchdog Timer are
reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared,
and the “wdt_fault” signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on
the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
6500C–ATARM–8-Feb-11

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