ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 810

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.10 CE-ATA Operation
35.10.1
35.10.2
35.10.3
35.10.4
810
SAM3S Preliminary
Executing an ATA Polling Command
Executing an ATA Interrupt Command
Aborting an ATA Command
CE-ATA Error Recovery
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is
mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC
devices.
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The SPCMD field of the
HSMCI_CMDR must be set to 3 to issue the CE-ATA completion Signal Disable Command.
Several methods of ATA command failure may occur, including:
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a timeout
is:
• GO_IDLE_STATE (CMD0): used for hard reset.
• STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be
• FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access
• RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the
• RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
• Issue the command completion signal disable if nIEN was cleared to zero and the
aborted.
only.
control/status registers.
RW_MULTIPLE_BLOCK (CMD61) response has been received.
with nIEN field set to zero to enable the command completion signal in the device.
6500C–ATARM–8-Feb-11