ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 105
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 105 of 1118
- Download datasheet (24Mb)
10.13.1
10.13.1.1
10.13.1.2
10.13.1.3
6500C–ATARM–8-Feb-11
ADD, ADC, SUB, SBC, and RSB
Syntax
Operation
Restrictions
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
where:
op
S
result of the operation, see
cond
Rd
Rn
Operand2
imm12
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is
clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see
page
See also
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the
SUB syntax that uses the imm12 operand.
In these instructions:
• Operand2 must not be SP and must not be PC
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
107.
ADD
ADC
SUB
SBC
RSB
“ADR” on page
is one of:
Add.
Add with Carry.
Subtract.
Subtract with Carry.
Reverse Subtract.
is an optional suffix. If S is specified, the condition code flags are updated on the
is an optional condition code, see
is the destination register. If Rd is omitted, the destination register is Rn.
is the register holding the first operand.
is a flexible second operand.
See
is any value in the range 0-4095.
“Flexible second operand” on page 80
88.
“Conditional execution” on page
“Conditional execution” on page
; ADD and SUB only
for details of the options.
SAM3S Preliminary
84.
“Multiword arithmetic examples” on
84.
105
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