ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 1103

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6500C–ATARM–8-Feb-11
Doc. Rev.
6500B
Comments
RTC:
Section 14.4.2
SPI:
Section 30.8.9 “SPI Chip Select
added a note concerning data transfer.
Section 30.8.3 “SPI Receive Data
added a note on requirements.
Section 30.7.3.5 “Peripheral
TC:
Figure 34-3, "Clock Selection"
Section 34.7.2 “TC Block Mode
TXC2XC2S bitfield description tables.
Section 34.7.11 “TC Channel Mode Register: Waveform
Selection”
UART:
“CD: Clock
Figure 32-1, "UART Functional Block
UDP:
Section 37.3.1 “Signal
Section 37.4.1 “I/O
Global; references to “DP”, “DM”, changed to “DPP”, “DMM”.
Table 37-6, “Register
w/endpoint info.
Section 37.7.10 “UDP Endpoint Control and Status
USART:
“CD: Clock
Section 33.7.1 “Baud Rate
Section 33.7.1.3 “Baud Rate in Synchronous Mode or SPI
Confusing text references to “DMAC/PDC“ replaced by PDC.
bitfield description
Divisor”, bitfield description updated in UART_BRGR.
Divider”, bitfield description, baud rate formula corrected in US_BRGR.
“Interrupt”, updated.
Lines”, updated.
Mapping”, Offsets and Names for UDP_CSRY and Endpoint UDP_FDRY updated
Description”, added to datasheet.
Generator”, updated “
Selection”, added a paragraph at the end of the section.
and
Register”, updated Name and Description columns in TC0XC0S, TXC1XC1S,
Register”, after bit description
Register”, after bit description
Figure 34-5, "Capture
Diagram", updated.
The frequency of the signal provided on SCK...”
Register”, code updated.
Mode”In the TC_CMR register
Mode", updated w/ synchronous edge detection.
Mode”, updated, “the receive part limits the SCK...”
“SCBR: Serial Clock Baud Rate” on page
“PCS: Peripheral Chip Select” on page
SAM3S Preliminary
“WAVSEL: Waveform
603,
611,
Change
Request
Ref.
7071
7247
7263
7096
7167
7190
7187
7285
rfo
6773
rfo
6895
6896
7186
7096
7284
1103