ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 63

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.6
10.6.1
10.6.1.1
10.6.1.2
10.6.1.3
10.6.1.4
10.6.2
10.6.2.1
10.6.2.2
10.6.2.3
6500C–ATARM–8-Feb-11
Exception model
Exception states
Exception types
Inactive
Pending
Active
Active and pending
Reset
Non Maskable Interrupt (NMI)
Hard fault
This section describes the exception model.
Each exception is in one of the following states:
The exception is not active and not pending.
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the correspond-
ing interrupt to pending.
An exception that is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case both
exceptions are in the active state.
The exception is being serviced by the processor and there is a pending exception from the
same source.
The exception types are:
Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at
any point in an instruction. When reset is deasserted, execution restarts from the address pro-
vided by the reset entry in the vector table. Execution restarts as privileged execution in Thread
mode.
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is
the highest priority exception other than reset. It is permanently enabled and has a fixed priority
of -2.
NMIs cannot be:
A hard fault is an exception that occurs because of an error during exception processing, or
because an exception cannot be managed by any other exception mechanism. Hard faults have
a fixed priority of -1, meaning they have higher priority than any exception with configurable
priority.
• Masked or prevented from activation by any other exception.
• Preempted by any exception other than Reset.
SAM3S Preliminary
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