ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 874

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1BA-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1BA-AUR
Manufacturer:
Atmel
Quantity:
10 000
36.6.5.5
874
SAM3S Preliminary
Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the
channel 0 is enabled (see
To prevent unexpected comparison match, the user must use the
Update Register”
and PWM_CMPxMUPD) to change respectively the comparison values and the comparison
configurations while the channel 0 is still enabled. These registers hold the new values until the
end of the comparison update period (when CUPRCNT is equal to CUPR in
x Mode Register”
ues for the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be fol-
lowed by a write of the register PWM_CMPxMUPD.
Note:
Figure 36-19. Synchronized Update of Comparison Values and Configurations
If the update registers PWM_CMPxVUPD and PWM_CMPxMUPD are written several times
between two updates, only the last written value are taken into account.
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPxM written
End of channel0 PWM period and
end of Comparison Update Period
(PWM_CMPxM)) and the end of the current PWM period, then update the val-
and the
Section 36.6.3 “PWM Comparison
“PWM Comparison x Mode Update Register”
PWM_CMPxVUPD Value
Comparison Value
for comparison x
PWM_CMPxV
User's Writing
Units”).
PWM_CMPxMUPD Value
Comparison configuration
“PWM Comparison x Value
for comparison x
User's Writing
PWM_CMPxM
(PWM_CMPxVUPD
“PWM Comparison
6500C–ATARM–8-Feb-11

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