ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 539

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.5
Table 29-1.
29.6
29.6.1
29.6.2
29.6.3
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Pin Name
RF
RK
RD
TF
TK
TD
Pin Name List
Product Dependencies
I/O Lines
Power Management
Interrupt
I/O Lines Description
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
Table 29-2.
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
The SSC interface has an interrupt line connected to the Nested Vector Interrupt Controller
(NVIC). Handling interrupts requires programming the NVIC before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-
vice routine can get the interrupt origin by reading the SSC interrupt status register.
Table 29-3.
Instance
Instance
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
SSC
SSC
SSC
SSC
SSC
SSC
SSC
I/O Lines
Peripheral IDs
22
ID
Signal
RD
RK
RF
TD
TF
TK
SAM3S Preliminary
SAM3S Preliminary
I/O Line
PA18
PA20
PA19
PA17
PA15
PA16
Input/Output
Input/Output
Input/Output
Input/Output
Output
Type
Input
Peripheral
A
A
A
A
A
A
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