ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 87

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.12 Memory access instructions
6500C–ATARM–8-Feb-11
Table 10-17
Table 10-17. Memory access instructions
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDREX{type}
POP
PUSH
STM{mode}
STR{type}
STR{type}
STR{type}T
STREX{type}
shows the memory access instructions:
Brief description
Load PC-relative address
Clear Exclusive
Load Multiple registers
Load Register using immediate
offset
Load Register using register offset
Load Register with unprivileged
access
Load Register using PC-relative
address
Load Register Exclusive
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate
offset
Store Register using register offset
Store Register with unprivileged
access
Store Register Exclusive
See
“ADR” on page 88
“CLREX” on page 102
“LDM and STM” on page 97
“LDR and STR, immediate offset” on
page 89
“LDR and STR, register offset” on page
92
“LDR and STR, unprivileged” on page 94
“LDR, PC-relative” on page 95
“LDREX and STREX” on page 100
“PUSH and POP” on page 99
“PUSH and POP” on page 99
“LDM and STM” on page 97
“LDR and STR, immediate offset” on
page 89
“LDR and STR, register offset” on page
92
“LDR and STR, unprivileged” on page 94
“LDREX and STREX” on page 100
SAM3S Preliminary
87