ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 439

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.14 Clock Switching Details
26.14.1
6500C–ATARM–8-Feb-11
Master Clock Switching Timings
Table 26-1
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock
has to be added.
Table 26-1.
Notes:
Table 26-2.
To
Main Clock
SLCK
PLL Clock
To
PLLA Clock
PLLB Clock
1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
and
From
Clock Switching Timings (Worst Case)
Clock Switching Timings between Two PLLs (Worst Case)
From
Table 26-2
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
give the worst case timings required for the Master Clock to switch
4.5 x SLCK
4 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x PLLB Clock +
1.5 x PLLB Clock
–
PLLA Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
SAM3S Preliminary
PLLBCOUNT x SLCK
2.5 x PLLB Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
PLLB Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
3 x PLL Clock +
3 x PLL Clock +
1 x Main Clock
4 x SLCK +
4 x SLCK +
PLL Clock
5 x SLCK
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