ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 490
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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SAM3S Preliminary
SAM3S Preliminary
sive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input
Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an
input only, controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Addi-
tional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable
Register). The current state of this selection can be read through the PIO_AIMMR (Additional
Interrupt Modes Mask Register)
These Additional Modes are:
In order to select an Additional Interrupt Mode:
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Inter-
rupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller
interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired
together to generate a single interrupt signal to the Nested Vector Interrupt Controller (NVIC).
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is
enabled on a “Level”, the interrupt is generated as long as the interrupt source is not cleared,
even if some read accesses in PIO_ISR are performed.
• Rising Edge Detection
• Falling Edge Detection
• Low Level Detection
• High Level Detection
• The type of event detection (Edge or Level) must be selected by writing in the set of registers;
• The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected
PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable
respectively, the Edge and Level Detection. The current status of this selection is accessible
through the PIO_ELSR (Edge/Level Status Register).
by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and
PIO_REHLSR (Rising Edge/High Level Select Register) which allow to select Falling or
Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or Low Level Detection (if
Level is selected in the PIO_ELSR). The current status of this selection is accessible through
the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
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