ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 934

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 37-8. Data IN Transfer for Ping-pong Endpoint
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TXPKTRDY Flag
(UDP_MCSRx)
FIFO (DPR)
Bank 0
FIFO (DPR)
USB Bus
Packets
TXCOMP Flag
(UDP_CSRx)
Bank 1
SAM3S Preliminary
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Set by Firmware,
Data Payload Written in FIFO Bank 0
When using a ping-pong endpoint, the following procedures are required to perform Data IN
transactions:
Warning: There is software critical path due to the fact that once the second bank is filled, the
driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP
is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the
bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second
5. The microcontroller is notified that the first Bank has been released by the USB device
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB
7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay-
Data IN
PID
be cleared in the endpoint’s UDP_CSRx register.
zero or more byte values in the endpoint’s UDP_FDRx register.
FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register.
data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the
endpoint’s UDP_FDRx register.
when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending
while TXCOMP is being set.
device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end-
point’s UDP_CSRx register.
load to be sent
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
Written by
Microcontroller
Read by USB Device
Data IN
Cleared by USB Device,
Data Payload Fully Transmitted
.
Set by USB
Device
ACK
PID
Interrupt Cleared by Firmware
Data IN
PID
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
Written by
Microcontroller
Set by Firmware,
Data Payload Written in FIFO Bank 1
Read by USB Device
Data IN
Set by USB Device
6500C–ATARM–8-Feb-11
ACK
PID