ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 489

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-5. Input Glitch Filter Timing
Figure 28-6. Input Debouncing Filter Timing
28.5.10
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Divided Slow Clock
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
if PIO_IFSR = 0
if PIO_IFSR = 1
Input Edge/Level Interrupt
PIO_PDSR
PIO_PDSR
Pin Level
MCK
up to 2 cycles Tmck
not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to
be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out,
its duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs
on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt
detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a
level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two succes-
1 cycle
1 cycle
up to 2 cycles Tmck
PIO_IFCSR = 1
PIO_IFCSR = 0
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 1.5 cycles
1 cycle
up to 2.5 cycles
up to 2 cycles Tmck
2 cycles
SAM3S Preliminary
SAM3S Preliminary
Figure 28-5
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles
and
1 cycle
1 cycle
Figure
up to 2 cycles Tmck
28-6.
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