ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 925

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37. USB Device Port (UDP)
37.1
Table 37-1.
Note:
37.2
6500C–ATARM–8-Feb-11
Endpoint Number
0
1
2
3
4
5
6
7
Description
1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode.
Embedded Characteristics
USB Endpoint Description
Mnemonic
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed
device specification.
Each endpoint can be configured in one of several USB transfer types. It can be associated with
one or two banks of a dual-port RAM used to store the current data payload. If two banks are
used, one DPR bank is read or written by the processor, while the other is read or written by the
USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device
maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of
DPR.
Suspend and resume are automatically detected by the USB device, which notifies the proces-
sor by raising an interrupt. Depending on the product, an external signal can be used to send a
wake up to the USB host controller.
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
• USB V2.0 full-speed compliant,12 Mbits per second.
• Embedded USB V2.0 full-speed transceiver
• Embedded 2688-byte dual-port RAM for endpoints
• Eight endpoints
• Suspend/resume logic
• Integrated Pull-up on DDP
• Pull-down resistor on DDM and DDP when disabled
– Endpoint 0: 64 bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 512 bytes ping-pong
– Endpoint 6 and 7: 64 bytes ping-pong
– Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
Dual-Bank
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
Max. Endpoint Size
512
512
64
64
64
64
64
64
SAM3S Preliminary
Control/Bulk/Interrupt
Control/Bulk/Interrupt
Bulk/Iso/Interrupt
Bulk/Iso/Interrupt
Bulk/Iso/Interrupt
Bulk/Iso/Interrupt
Bulk/Iso/Interrupt
Bulk/Iso/Interrupt
Endpoint Type
925