ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 171

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.21.6
• VECTKEYSTAT
Register Key:
Reads as 0xFA05
• VECTKEY
Register key:
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANESS
RO
Data endianness bit:
0 = Little-endian
ENDIANESS is set from the BIGEND configuration signal during reset.
• PRIGROUP
R/W
Interrupt priority grouping field. This field determines the split of group priority from subpriority, see
172.
• SYSRESETREQ
WO
System reset request:
0 = no effect
1 = asserts a proc_reset_signal.
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
6500C–ATARM–8-Feb-11
ENDIANESS
31
23
15
7
Application Interrupt and Reset Control Register
30
22
14
6
The AIRCR provides priority grouping control for the exception model, endian status for data
accesses, and reset control of the system. See the register summary in
164
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor
ignores the write.
The bit assignments are:
and
Reserved
Table 10-33 on page 191
29
21
13
5
On Read: VECTKEYSTAT, On Write: VECTKEY
On Read: VECTKEYSTAT, On Write: VECTKEY
Reserved
28
20
12
4
for its attributes.
27
19
11
3
SYSRESETREQ
26
18
10
2
SAM3S Preliminary
PRIGROUP
VECTCLR-
ACTIVE
25
17
9
1
“Binary point” on page
Table 10-30 on page
VECTRESET
24
16
8
0
171