ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 1018

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40.6
40.6.1
40.6.2
40.6.3
40.6.4
40.6.5
1018
Functional Description
SAM3S Preliminary
Digital-to-Analog Conversion
Conversion Results
Conversion Triggers
Conversion FIFO
Channel Selection
The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is named DACC
Clock. Once a conversion starts the DACC takes 25 clock periods to provide the analog result on the
selected analog output.
When a conversion is completed, the resulting analog value is available at the selected DACC channel out-
put and the EOC bit in the
Reading the DACC_ISR register clears the EOC bit.
In free running mode, conversion starts as soon as at least one channel is enabled and data is written in
the
the corresponding analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free running mode.
A 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the
accept conversion requests by writing data into
converted immediately are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
The WORD field of the
for writing into the FIFO.
In half-word transfer mode only the 16 LSB of DACC_CDR data are taken into account, DACC_CDR[15:0]
is stored into the FIFO.
DACC_CDR[11:0] field is used as data and the DACC_CDR[15:12] bits are used for channel selection if the
TAG field is set in DACC_MR register.
In word transfer mode each time the DACC_CDR register is written 2 data items are stored in the FIFO. The
first data item sampled for conversion is DACC_CDR[15:0] and the second DACC_CDR[31:16].
Fields DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG field is set in
DACC_MR register.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO data.
There are two means by which to select the channel to perform data conversion.
• By default, to select the channel where to convert the data, is to use the USER_SEL field of
• A more flexible option to select the channel for the data to be converted to is to use the tag
the
with the USER_SEL field.
mode, setting the TAG field of the
DACC_CDR[13:12] which are otherwise unused, are employed to select the channel in the
same way as with the USER_SEL field. Finally, if the WORD field is set, the 2 bits,
DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits,
DACC_CDR[29:28] for channel selection of the second data.
DACC Conversion Data
DACC Mode
Register. Data requests will merely be converted to the channel selected
DACC Mode Register
DACC Interrupt Status
Register, then 25 DACC Clock periods later, the converted data is available at
DACC Interrupt Status Register
DACC Mode Register
allows the user to switch between half-word and word transfer
DACC Conversion Data
Register, is set.
to 1. In this mode the 2 bits,
is active the DAC Controller is ready to
Register. Data which cannot be
6500C–ATARM–8-Feb-11