ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 151

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.20 Nested Vectored Interrupt Controller
Table 10-27. NVIC register summary
1.
10.20.1
6500C–ATARM–8-Feb-11
Address
0xE000E100-
0xE000E104
0xE000E180-
0xE000E184
0xE000E200-
0xE000E204
0xE000E280-
0xE000E284
0xE000E300-
0xE000E304
0xE000E400-
0xE000E41C
0xE000EF00
See the register description for more information.
The CMSIS mapping of the Cortex-M3 NVIC registers
Name
ISER0-
ISER1
ICER0-
ICER1
ISPR0-
ISPR1
ICPR0-
ICPR1
IABR0-
IABR1
IPR0-
IPR8
STIR
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling. The
hardware implementation of the NVIC registers is:
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the
CMSIS:
• 1 to 35 interrupts.
• A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower
• Level and pulse detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields.
• Interrupt tail-chaining.
• the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to
priority, so level 0 is the highest interrupt priority.
arrays of 32-bit integers, so that:
– the array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1
– the array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1
– the array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1
– the array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1
– the array IABR[0] to IABR[1] corresponds to the registers IABR0-IABR1
Type
RW
RW
RW
RW
RO
RW
WO
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Configurable
(1)
Reset
value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
“Interrupt Set-enable Registers” on page 153
“Interrupt Clear-enable Registers” on page 154
“Interrupt Set-pending Registers” on page 155
“Interrupt Clear-pending Registers” on page 156
“Interrupt Active Bit Registers” on page 157
“Interrupt Priority Registers” on page 158
“Software Trigger Interrupt Register” on page
161
SAM3S Preliminary
151