ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 660

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32.5.2.2
32.5.2.3
660
660
SAM3S Preliminary
SAM3S Preliminary
Start Detection and Data Sampling
Receiver Ready
The programmer can also put the receiver in its reset state by writing UART_CR with the bit
RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled,
whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
The UART only supports asynchronous operations, and this affects only its receiver. The UART
receiver detects the start of a received character by sampling the URXD signal until it detects a
valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for
more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is
longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit
period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period)
so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling
point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 32-3. Start Bit Detection
Figure 32-4. Character Reception
When a complete character is received, it is transferred to the UART_RHR and the RXRDY sta-
tus bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register UART_RHR is read.
Sampling Clock
Baud Rate
Example: 8-bit, parity enabled 1 stop
Sampling
URXD
Clock
URXD
0.5 bit
period
True Start Detection
period
1 bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
D7
Parity Bit
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
D0
Stop Bit