ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 1098

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

44.2
44.2.1
44.2.1.1
44.2.1.2
44.2.1.3
44.2.2
44.2.2.1
44.2.2.2
1098
Errata Revision A Parts
SAM3S Preliminary
Flash Memory
Analog-to-Digital Converter (ADC)
FLASH: Flash Reading in 64-bit mode
FLASH: Flash issue running at frequency lower than 5 MHz
FLASH: Flash Programming
ADC: Comparison Window, High Threshold Value
ADC: End of Conversion (EOC) Flag
Revision A parts Chip IDs are as follows:
Higher power consumption than expected can be seen when reading Flash in 64-bit mode.
Use 128-bit mode instead.
When the system clock (MCK) is lower than 5 MHz with 2 Wait States (WS) programmed in the
EEFC_FMR, the Cortex fetches erroneous instructions.
Do not use 2 WS when running at a frequency lower than 5 MHz.
When writing data into the Flash memory plane (either through the EEFC, using the IAP function
or FFPI), the data may not be correctly written (i.e the data written is not the one expected).
Set the number of Wait States (WS) at 6 (FWS = 6) during the programming.
High threshold bits[27:16] of the ADC Compare Window Register (ADC_CWR) are not function-
ally read/write and return 0 when ADC_CWR register is read. However, the high threshold value
is correctly registered and behaves accordingly.
Ignore the read value of ADC_CWR high threshold bits [27:16].
Performing a software reset (SWRST bit in ADC_CR) does not reset the EOCx flags of the ADC
Interrupt Status Register.
Reading the ADC_CDRx channels clears the corresponding EOCx flag.
• SAM3S4C (Rev A)
• SAM3S2C (Rev A)
• SAM3S1C (Rev A)
• SAM3S4B (Rev A)
• SAM3S2B (Rev A)
• SAM3S1B (Rev A)
• SAM3S4A (Rev A)
• SAM3S2A (Rev A)
• SAM3S1A (Rev A)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
0x28900960
0x289A0760
0x28990560
0x28800960
0x288A0760
0x28890560
0x28A00960
0x28AA0760
0x28A90560
6500C–ATARM–8-Feb-11