ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 370
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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23.8.1.5
23.8.2
23.8.2.1
23.8.2.2
370
SAM3S Preliminary
Read Mode
Null Pulse
Read is Controlled by NRD (READ_MODE = 1):
Read is Controlled by NCS (READ_MODE = 0)
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register
of the corresponding chip select indicates which signal of NRD and NCS controls the read
operation.
Figure 23-7
data is available t
In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data
is available with the rising edge of NRD. The SMC samples the read data internally on the rising
edge of Master Clock that generates the rising edge of NRD, whatever the programmed wave-
form of NCS may be.
Figure 23-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
Figure 23-8
falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sam-
pled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by
NCS): the SMC internally samples the data on the rising edge of Master Clock that generates
the rising edge of NCS, whatever the programmed waveform of NRD may be.
A[23:0]
D[7:0]
MCK
NRD
NCS
shows the waveforms of a read operation of a typical asynchronous RAM. The read
shows the typical read cycle of an LCD module. The read data is valid t
PACC
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD.
t
PACC
Data Sampling
6500C–ATARM–8-Feb-11
PACC
after the
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