ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 649

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

31.11.6
Name:
Addresses: 0x40018020 (0), 0x4001C020 (1)
Access:
Reset:
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 640
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 640
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
6500C–ATARM–8-Feb-11
TXBUFE
31
23
15
–
–
7
–
and
and
TWI Status Register
TWI_SR
Read-only
0x0000F009
Figure 31-31 on page
Figure 31-31 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
640.
640.
29
21
13
–
–
5
Figure 31-8 on page
Figure 31-10 on page
Figure 31-26 on page
ENDRX
SVACC
Figure 31-28 on page
Figure 31-8 on page 621
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
621.
622.
636,
638,
and in
Figure 31-29 on page
Figure 31-29 on page
SCLWS
TXRDY
26
18
10
–
–
2
Figure 31-10 on page
SAM3S Preliminary
ARBLST
RXRDY
25
17
–
–
9
1
639,
639,
622.
Figure 31-30 on
Figure 31-30 on
TXCOMP
NACK
24
16
–
–
8
0
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