ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 80

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.11.3
10.11.3.1
10.11.3.2
10.11.3.3
80
SAM3S Preliminary
Flexible second operand
Constant
Instruction substitution
Register with optional shift
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be
1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3
processor only supports Thumb instructions.
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
You specify an Operand2 constant in the form:
where constant can be:
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS,
EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is
greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
Your assembler might be able to produce an equivalent instruction in cases where you specify a
constant that is not permitted. For example, an assembler might assemble the instruction CMP
Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
You specify an Operand2 register in the form:
where:
Rm
shift
•
•
• any constant that can be produced by shifting an 8-bit value left by any number of bits within
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
“Constant”
“Register with optional shift” on page 80
a 32-bit word
#constant
Rm {, shift}
ASR #n
LSL #n
is the register holding the data for the second operand.
is an optional shift to be applied to Rm. It can be one of:
arithmetic shift right n bits, 1 ≤ n ≤ 32.
logical shift left n bits, 1 ≤ n ≤ 31.
6500C–ATARM–8-Feb-11