EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 97

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–18. Multiply Accumulate Mode Shown for Half-DSP Block
Note to
(1) Block output for saturation overflow of chainout.
December 2010 Altera Corporation
Figure
Multiply Accumulate Mode
accum_sload
4–18:
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
In multiply accumulate mode, the second-stage adder is configured as a 44-bit
accumulator or subtractor. The output of the DSP block is looped back to the
second-stage adder and added or subtracted with the two outputs of the first-stage
adder block according to
Figure 4–18
A single DSP block can implement up to two independent 44-bit accumulators.
Use the dynamic accum_sload control signal to clear the accumulation. A logic 1
value on the accum_sload signal synchronously loads the accumulator with the
multiplier result only, and a logic 0 enables accumulation by adding or subtracting
the output of the DSP block (accumulator feedback) to the output of the multiplier
and first-stage adder.
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
shows the DSP block configured to operate in multiply accumulate mode.
output_saturate
+
+
output_round
Equation 4–3 on page
signa
signb
+
Arria II Device Handbook Volume 1: Device Interfaces and Integration
4–5.
chainout_sat_overflow (1)
44
result[ ]
4–25