EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 412

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–26
Figure 1–28. CDR Block
Arria II Device Handbook Volume 2: Transceivers
Global Clock Line
Dedicated refclk0
Dedicated refclk1
PLL Cascade Clock
ITB Clock Lines
rx_datain
6
rx_locktorefclk
rx_locktodata
rx_freqlocked
signal detect
1
1
In PCIe mode, you can enable the optional signal threshold detection circuitry by
leaving the Force signal detection option unchecked in the ALTGX MegaWizard
Plug-In Manager.
The appropriate signal detect threshold level that complies with the PCIe compliance
parameter VRX-IDLE-DETDIFFp-p is pending characterization.
If you enable the Force signal detection option in the ALTGX MegaWizard Plug-In
Manager, the rx_signaldetect signal is always asserted high, irrespective of the
signal level on the receiver input buffer. When enabled, this option senses whether the
signal level present at the receiver input buffer is above the signal detect threshold
voltage that you specified in the What is the signal detect and signal loss threshold?
option in the ALTGX MegaWizard Plug-In Manager.
The rx_signaldetect signal is also used by the LTR/LTD controller in the receiver
CDR to switch between LTR and LTD lock modes. When the signal threshold
detection circuitry de-asserts the rx_signaldetect signal, the LTR/LTD controller
switches the receiver CDR from lock-to-data (LTD) to lock-to-reference (LTR) lock
mode.
CDR
Each Arria II GX and GZ receiver channel has an independent CDR unit to recover the
clock from the incoming serial data stream. High-speed and low-speed recovered
clocks are used to clock the receiver PMA and PCS blocks.
block.
/1, /2, /4
/2
Frequency
Controller
LTR/LTD
Detector
Detector
Phase
Phase
(PFD)
(PD)
Up
Up
Down
Down
Charge Pump
Loop Filter
Chapter 1: Transceiver Architecture in Arria II Devices
+
Clock and Data Recovery (CDR) Unit
Controlled
Oscillator
Voltage
Detect
(V
Lock
/M
CO
)
Figure 1–28
December 2010 Altera Corporation
/L
Receiver Channel Datapath
shows the CDR
High-Speed
Recovered Clock
rx_pll_locked
Low-Speed
Recovered Clock