EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 483

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transceiver Port List
Table 1–26. ALTGX Megafunction Rate Match (Clock Rate Compensation) FIFO Ports for Arria II Devices (Part 2 of 2)
Table 1–27. ALTGX Megafunction 8B/10B Decoder Ports for Arria II Devices
December 2010 Altera Corporation
rx_rmfifoempty
rx_rmfifofull
rx_ctrldetect
rx_disperr
rx_errdetect
rx_runningdisp
Port Name
Port Name
Table 1–27
megafunction. These ports are 1-bit wide with 8-bit channel width and 2-bit wide
with 16-bit channel width.
Input/Output
Input/Output
Output
Output
Output
Output
Output
Output
lists the 8B/10B decoder port names and descriptions for the ALTGX
Receiver control code indicator.
A high level indicates that the associated received code group is a control
(/Kx.y/) code group. A low level indicates that the associated received code
group is a data (/Dx.y/) code group.
8B/10B disparity error indicator port.
A high level indicates that a disparity error was detected on the associated
received code group.
8B/10B code group violation or disparity error indicator.
A high level indicates that a code group violation or disparity error was detected
on the associated received code group. Use with the rx_disperr signal to
differentiate between a code group violation and/or a disparity error as follows:
[rx_errdetect: rx_disperr]
2’b00—no error
2’b10—code group violation
2’b11—disparity error or both
8B/10B running disparity indicator.
A high level indicates that data on the rx_dataout port was received with a
negative running disparity. A low level indicates that data on the rx_dataout
port was received with a positive running disparity.
Asynchronous rate match FIFO empty status indicator. A high level indicates
that the rate match FIFO is empty.
This signal is driven for a minimum of two recovered clock cycles in
configurations without byte serializer and a minimum of three recovered clock
cycles in configurations with byte serializer. You must then assert the
rx_digitalreset signal to reset this signal.
Asynchronous rate match FIFO full status indicator. A high level indicates that
the rate match FIFO is full.
This signal is driven for a minimum of two recovered clock cycles in
configurations without byte serializer and a minimum of three recovered clock
cycles in configurations with byte serializer. You must then assert the
rx_digitalreset signal to reset this signal.
Description
Description
Arria II Device Handbook Volume 2: Transceivers
1–97