EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 217

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface
December 2010 Altera Corporation
Using the R
in Arria II GZ Devices
1
1
You can use the DQS/DQSn pins in some of the ×4 groups as R
in the pin table). You cannot use a ×4 DQ/DQS group for memory interfaces if any of
its pin members are used as R
use the ×8/×9 group that includes this ×4 DQ/DQS group, if either of the following
applies:
■
■
You can use the ×8/×9 group because a DQ/DQS ×8/×9 group actually comprises 12
pins, because the groups are formed by stitching two DQ/DQS groups in ×4 mode
with six pins each (refer to
consists of one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose
your pin assignment carefully, you can use the two extra pins for R
DDR3 SDRAM interface, you must use differential DQS, which means that you only
have one extra pin. In this case, pick different pin locations for the R
(for example, in the bank that contains the address and command pins).
You cannot use the R
×9 QDR II+/QDR II SRAM devices, because the R
with the CQn pins. In this case, pick different pin locations for R
avoid conflict with memory interface pin placement. You have the choice of placing
the R
command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQ/DQS groups that include the
×4 groups whose pins are being used as R
extra pins that can be used as DQS pins.
For ×8, ×16/×18, or ×32/×36 DQ/DQS groups whose members are used for R
R
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
This implementation combines ×16/×18 DQ/DQS groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups, and
the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The CQ/CQn
signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in
the FPGA. This is the only connection on the board that you must change for this
implementation. Other QDR II+/QDR II SRAM interface rules for Arria II devices
also apply for this implementation.
The ALTMEMPHY megafunction and UniPHY IP core do not use the QVLD signal, so
you can leave the QVLD signal unconnected as in any QDR II+/QDR II SRAM
interfaces in Arria II devices.
DN
UP
You are not using DM pins with your differential DQS pins
You are not using complementary or differential DQS pins
, you must assign DQS and DQ pins manually. The Quartus
UP
and R
and R
DN
DN
pins in the data-write group or in the same bank as the address and
Pins in a DQ/DQS Group Used for Memory Interfaces
UP
and R
Table 7–1 on page
UP
DN
and R
pins shared with DQ/DQS group pins when using
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DN
pins for OCT calibration. You may be able to
UP
and R
7–5). A typical ×8 memory interface
UP
DN
and R
pins, because there are enough
DN
pins are dual purpose
UP
®
UP
and R
II software might
UP
and R
UP
and R
and R
DN
DN
pins (listed
DN
pins to
DN
UP
. In a
pins
and
7–21