EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 124

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–20
Table 5–13. PLL Features in Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
C (output) counters
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock
tracking
PLL cascading
Compensation modes
PLL drives DIFFCLK and
LOADEN
VCO output drives DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
Notes to
(1) PLL_5 and PLL_6 do not have dedicated clock outputs.
(2) The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in PLL_1 and PLL_3 of EP2AGX95,
(3) This is applicable only if the input clock jitter is within the input jitter tolerance specifications.
(4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Arria II device
EP2AGX125, EP2AGX190, and EP2AGX260 devices.
can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and C counter
value.
Table
Feature
5–13:
Table 5–13
1 single-ended or 1 differential
3 single-ended or 3 differential
4 single-ended or 2 differential
Through GCLK and RCLK and
between the general-purpose
All except external feedback
PLL and transceiver PLL is
adjacent PLLs. Cascading
lists the PLL features in Arria II devices.
supported in PLL_1 and
dedicated path between
Down to 96.125 ps
mode when you use
Arria II GX PLLs
differential I/Os
pairs (1),
pin pairs
1 to 512
Yes
PLL_4.
pair
Yes
Yes
Yes
Yes
Yes
No
7
(3)
(2)
(5)
Single-ended or differential
6 single-ended or 4 single-
Through GCLK and RCLK
ended and 1 differential
between adjacent PLLs
Down to 96.125 ps
network compensation
All except LVDS clock
and a dedicated path
differential pin pairs
4 single-ended or 2
Top/Bottom PLLs
1 to 512
Yes
Chapter 5: Clock Networks and PLLs in Arria II Devices
pair
Yes
Yes
Yes
10
No
No
(3)
Arria II GZ PLLs
(5)
December 2010 Altera Corporation
2 single-ended or 1 differential
4 single-ended or 2 differential
Through GCLK and RCLK and
All except external feedback
dedicated path between
Down to 96.125 ps
mode when you use
adjacent PLLs
Single-ended only
Left/Right PLLs
differential I/Os
PLLs in Arria II Devices
pin pairs
1 to 512
Yes
pair
Yes
Yes
Yes
Yes
Yes
7
(3)
(4)
(5)