EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 472

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–86
Figure 1–82. Reverse Serial Loopback Datapath
Note to
(1) The only active block of the transmitter channel is the transmitter buffer.
Arria II Device Handbook Volume 2: Transceivers
Fabric
FPGA
Figure
Reverse Serial Loopback
1–82:
When you enable serial loopback, the transmitter channel sends the data to both the
tx_dataout output port and the receiver channel. The differential output voltage on
the tx_dataout ports is based on the selected V
received by the receiver CDR and then timed again through different clock domains.
You must provide an alignment pattern for the word aligner to enable the receiver
channel to retrieve the byte boundary.
Reverse serial loopback is available in Basic functional mode only and is often
implemented when using a bit error rate tester (BERT) on the upstream transmitter. In
this mode, the data is received through the rx_datain port, timed again through the
receiver CDR, and sent out to the tx_dataout port. The received data is also available
to the FPGA logic. You can enable the reverse serial loopback option using the ALTGX
MegaWizard Plug-In Manager. Unlike other loopback modes, there is no dynamic pin
control to enable or disable reverse serial loopback.
Figure 1–82
You can change the output differential voltage on the transmitter buffer through the
ALTGX MegaWizard Plug-In Manager. However, you cannot alter the pre-emphasis
settings for the transmitter buffer.
tx_clkout[0]
Compensation
wrclk
TX Phase
shows the transceiver channel datapath for reverse serial loopback mode.
FIFO
rdclk
(Note 1)
/2
wrclk
Byte Serializer
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B/10B Encoder
Chapter 1: Transceiver Architecture in Arria II Devices
Low-Speed Parallel Clock
OD
settings. The looped back data is
Low-Speed Parallel Clock
Parallel Recovery Clock
December 2010 Altera Corporation
Transmitter Channel
Serial Clock
High-Speed
PMA
Receiver Channel
PMA
Reverse Serial
Loopback
Test Modes