EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 438

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–52
Arria II Device Handbook Volume 2: Transceivers
Figure 1–51
functional mode with an 8-bit wide PMA-PCS interface.
Figure 1–51. Transceiver Configurations in Basic Mode with an 8-Bit Wide PMA-to-PCS Interface
Notes to
(1) The 10-bit configuration is listed in
(2) The maximum data rate specification shown in
(3) When you enable byte SERDES, the maximum data is 3G; otherwise, it is 1.92G.
(Note 1)
Functional Mode
Data Rate (2)
Number of Channels
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES (3)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz) (2)
TX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
RX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
specifications for other speed grades offered, refer to the
Figure
shows the Arria II GX and GZ transceiver configurations allowed in Basic
1–51:
Disabled
Disabled
11 - 13
4 - 5.5
Figure
8-Bit
240
75-
Manual Alignment
Disabled
Disabled
1–52.
(16-Bit)
Disabled
16-Bit
187.5
4 - 5.5
Figure 1–51
37.5-
7 - 9
Enabled
Enabled
8 - 10
Disabled
16-Bit
187.5
Device Datasheet for Arria II Devices
Chapter 1: Transceiver Architecture in Arria II Devices
37.5-
4 - 5.5
is valid only for the -3 speed grade devices. For data rate
Basic 8-Bit PMA-PCS Interface Width
Disabled
Disabled
11 - 13
4 - 5.5
8-Bit
240
75-
Disabled
Disabled
(16-Bit)
Bit Slip
0.6 - 3.0 Gbps
×1, ×4, ×8
Disabled
Enabled
December 2010 Altera Corporation
16-Bit
187.5
37.5-
4 -5.5
7 - 9
Disabled
Disabled Disabled
8-Bit
3 - 4
240
3 - 4
75-
chapter.
Disabled
Disabled
Disabled
Enabled
Functional Modes
Enabled
3 - 4.5
16-Bit
187.5
3 - 4.5
37.5-