EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 325

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
Table 9–18. Dedicated JTAG Pins
December 2010 Altera Corporation
TDI
TDO
TMS
TCK
TRST
Note to
(1) The TRST pin is only available for Arria II GZ devices.
Pin Name
(1)
Table
9–18:
User Mode
N/A
N/A
N/A
N/A
N/A
Table 9–18
during configuration to prevent accidental loading of JTAG instructions. The TDI, TMS,
and TRST pins have weak internal pull-up resistors; the TCK pin has a weak internal
pull-down resistor (typically 25 kΩ ). If you plan to use the SignalTap™ embedded
logic array analyzer, you must connect the JTAG pins of the Arria II device to a JTAG
header on your board.
Test mode
Test clock
Test reset
(optional)
Pin Type
Test data
Test data
output
select
input
input
input
lists the dedicated JTAG pins. JTAG pins must be kept stable before and
Serial input pin for instructions as well as test and programming data. Data is
shifted on the rising edge of TCK. The TDI pin is powered by the V
supply for Arria II GX devices and the V
devices.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not
being shifted out of the device. The TDO pin is powered up by the V
power supply. For more information about connecting a JTAG chain with
multiple voltages across the devices in the chain, refer to the
Boundary-Scan Testing in Arria II Devices
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. TMS is evaluated on the rising edge of TCK.
Therefore, you must set up TMS before the rising edge of TCK. Transitions in the
state machine occur on the falling edge of TCK after the signal is applied to TMS.
The TMS pin is powered by the V
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Clock input to the BST circuitry. Some operations occur at the rising edge while
others occur at the falling edge. The TCK pin is powered by the V
power supply.
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to the IEEE Std. 1149.1 standard. The TRST pin is
powered the V
supply for Arria II GZ devices.
Hold TMS at one or keep TCK static while TRST is changed from 0 to 1.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting the TRST pin to GND. One kΩ pull-up resistor to V
you do not use the TRST pin.
CCIO
power supply for Arria II GX devices and the V
Arria II Device Handbook Volume 1: Device Interfaces and Integration
CCPD
Description
/V
CCIO
CCPD
chapter.
power supply.
power supply for Arria II GZ
JTAG
CCPD
CCPD
CCIO
CCPD
/V
power
power
CCIO
/V
CCPD
CCIO
9–45
if