EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 181

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
OCT Support
December 2010 Altera Corporation
f
R
All I/O banks in Arria II GX devices support input R
value of 100 Ω , as shown in
support R
V.
Arria II GZ column I/O banks and dedicated clock input pairs on the row I/O banks
do not support R
when both the V
Figure 6–7. Differential Input On-Chip Termination for Arria II Devices
For more information about R
with DPA in Arria II Devices
R
Arria II GZ devices support R
calibration is only supported for input configuration of input and bidirectional pins.
Output pin configurations do not support R
R
I/O standard of the pin where the R
Figure 6–8. R
D
T
T
OCT with calibration. When you use R
OCT with Calibration for Arria II GZ Devices
OCT for Arria II LVDS Input I/O Standard
D
OCT. You can enable R
T
Transmitter
OCT with Calibration for Arria II GZ Devices
CCIO
D
Transmitter
OCT. You can enable the Arria II GZ R
and V
CCPD
Figure
chapter.
T
D
OCT with calibration in all banks. R
OCT, refer to the
is set to 2.5 V.
6–7. However, not all input differential pins
D
T
Arria II Device Handbook Volume 1: Device Interfaces and Integration
OCT when both the V
Z
OCT is enabled.
Z
Z
O
O
O
= 50
= 50 Ω
= 50 Ω
T
OCT, the V
T
OCT with calibration.
V
REF
High-Speed Differential I/O Interfaces
D
CCIO
V
OCT with a nominal resistance
CCIO
GND
D
100
Arria II GZ OCT
100
of the bank must match the
CCIO
100 Ω
OCT in row I/O banks
Receiver
and V
Receiver
T
Figure 6–8
OCT with
CCPD
is set to 2.5
shows
6–23