EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 467

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–77. Transceiver Datapath in XAUI Mode
Notes to
(1) This allows the fabric-to-transceiver interface to run below the maximum interface frequency.
(2) The word aligner uses the automatic synchronization state machine (10-bit /K28.5/).
(3) This is running at half the rate of the data rate.
December 2010 Altera Corporation
Fabric
FPGA
16-Bit Interface at 156.25MHz (XAUI) or at 187.5 MHz (HiGig/HiGig+)
Figure
FPGA Fabric-Transceiver
Interface Clock
1–77:
Figure 1–77
XAUI mode.
Channel2
Channel0
Channel2
Channel0
/2
Channel3
Channel1
Channel3
tx_clkout[0]
Channel1
tx_clkout[0]
Compensation
Compensation
wrclk
wrclk
shows the ALTGX megafunction transceiver datapath when configured in
TX Phase
TX Phase
FIFO
FIFO
rdclk
rdclk
Input Reference Clock
Input Reference Clock
/2
/2
wrclk
wrclk
Byte Serializer
Byte Serializer
Low-Speed Parallel Clock from CMU 0 Clock Divider
Low-Speed Parallel Clock from CMU 0 Clock Divider
(1)
(1)
/2
/2
Receiver Channel PCS
Receiver Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
rdclk
rdclk
CMU1_PLL
CMU0_PLL
Low-Speed Parallel Clock from CMU 0 Clock Divider
Low-Speed Parallel Clock from CMU 0 Clock Divider
CMU0 Clock Divider
8B/10B Encoder
8B/10B Encoder
CMU1_Channel
CMU0_Channel
Arria II Device Handbook Volume 2: Transceivers
Ch0 Parallel Recovered Clock
Recovery Clock
Ch0 Parallel
10-Bit Interface
High-Speed Parallel Clock
Low-Speed Parallel Clock
Transmitter Channel
Transmitter Channel
Receiver Channel
Receiver Channel
Recovered Clock
Recovered Clock
Ch0 Parallel
Ch2 Parallel
PMA
PMA
PMA
PMA
1–81