EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 68

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–22
Figure 3–21. M9K and M144K Blocks Same Port Read-During Write: New Data Mode
Figure 3–22. M9K and M144K Blocks Same Port Read-During-Write: Old Data Mode
Arria II Device Handbook Volume 1: Device Interfaces and Integration
q_a (asynch)
q_a (asynch)
address
byteena
address
byteena
data_a
data_a
wrena
rdena
wrena
clk_a
rdena
clk_a
Figure 3–21
behavior in new data mode.
Figure 3–22
behavior in old data mode.
For MLABs, the output of the MLABs can only be set to don’t care in same-port
read-during-write mode. In this mode, the output of the MLABs is unknown during a
write cycle. There is a window near the falling edge of the clock during which the
output is unknown. Prior to that window, “old data” is read out; after that window,
“new data” is seen at the output.
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode which has one port
reading and the other port writing to the same address location with the same clock.
In this mode, you can choose “old data” or “don’t care” value as the output. In old
data mode, a read-during-write operation to different ports causes the RAM outputs
to reflect the “old data” at that address location. In don’t care mode, the same
operation results in a “don’t care” or “unknown” value on the RAM outputs.
shows sample functional waveforms of same-port read-during-write
shows sample functional waveforms of same-port read-during-write
A123
A123
01
01
A0 (old data)
XX23
B456
B456
10
10
A0
D
0A
old
B4XX
D
old
23
C789
C789
00
00
B423
XXXX
DDDD
DDDD
A1(old data)
DDDD
Chapter 3: Memory Blocks in Arria II Devices
A1
EEEE
0B
EEEE
11
11
DDDD
EEEE
December 2010 Altera Corporation
FFFF
FFFF
FFFF
EEEE
Design Considerations