EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 521

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–18. Four Identical Channels in a Transceiver Block for Example 1
December 2010 Altera Corporation
Channel PMA
Channel PMA
Channel PMA
Channel PMA
1
Transmitter
Divider Block
Transmitter
Divider Block
Transmitter
Divider Block
Transmitter
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
This configuration uses only one FPGA global, regional, and periphery clock resource
for tx_clkout[0].
If all four channels within a transceiver block are identical, the Quartus II software
automatically drives the write port of the transmitter phase compensation FIFO in
all four channels with tx_clkout[0], as shown in
tx_clkout[0] signal to clock the transmitter data and control logic for all four
channels in the FPGA fabric.
Example 1: Four Identical Channels in a Transceiver Block
Channel 3
Channel 2
Channel 1
Channel 0
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
CMU1 Block
CMU0 Block
Divider
Divider
CMU1
CMU0
Clock
Clock
/2
/2
/2
/2
/2
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
TX Phase
TX Phase
TX Phase
TX Phase
Input Reference Clock
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
tx_clkout[0]
Arria II Device Handbook Volume 2: Transceivers
Figure
FPGA Fabric
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
2–18. Use the
and Control
and Control
and Control
and Control
Channel 3
Channel 2
Channel 1
Channel 0
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
2–31