EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet
EP2AGX45DF29I5N
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EP2AGX45DF29I5N Summary of contents
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... Integration Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.0 Arria II Device Handbook ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Chapter 3. Memory Blocks in Arria II Devices Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Memory Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration Contents ...
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... High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24 Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25 Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26 Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28 DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30 Software Support for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32 Arria II Device Handbook Volume 1: Device Interfaces and Integration Contents December 2010 Altera Corporation ...
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... Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–48 Bypassing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–49 Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–49 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–52 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–52 Section II. I/O Interfaces for Arria II Devices Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration v ...
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... Pins in a DQ/DQS Group Used for Memory Interfaces in Arria II GZ Devices UP DN 7–21 Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . . . . . 7–21 Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22 Arria II External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24 Arria II Device Handbook Volume 1: Device Interfaces and Integration Contents December 2010 Altera Corporation ...
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... Using Both Corner PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36 Setting Up an LVDS Transmitter or Receiver Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36 Section III. System Integration for Arria II Devices Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 December 2010 Altera Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10 OD Arria II Device Handbook Volume 1: Device Interfaces and Integration vii ...
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... Arria II Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62 Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62 Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62 Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62 AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62 Flexible Security Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–63 Arria II Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64 Arria II Device Handbook Volume 1: Device Interfaces and Integration Contents December 2010 Altera Corporation ...
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... Insertion or Removal of an Arria II Device from a Powered-Up System . . . . . . . . . . . . . . . . . . . . . . 12–4 Hot-Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration ix ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Contents December 2010 Altera Corporation ...
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... Revised: Part Number: AIIGX51009-4.0 Chapter 10. SEU Mitigation in Arria II Devices Revised: Part Number: AIIGX51010-4.0 Chapter 11. JTAG Boundary-Scan Testing in Arria II Devices Revised: Part Number: AIIGX51011-4.0 December 2010 Altera Corporation December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 ...
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... Chapter 12. Power Management in Arria II Devices Revised: Part Number: AIIGX51012-3.0 Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Chapter Revision Dates December 2010 Altera Corporation ...
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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. December 2010 Altera Corporation Section I. Device Core for Arria II Devices Arria II Device Handbook Volume 1: Device Interfaces and Integration ® ...
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... I–2 Arria II Device Handbook Volume 1: Device Interfaces and Integration Section I: Device Core for Arria II Devices Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Emulated LVDS output support with a data rate 1152 Mbps Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 1: Overview for the Arria II Device Family ® (SRIO), Common Public Radio Interface (CPRI), OBSAI, ) and on-chip parallel (R S Arria II Device Feature ) termination with auto-calibration T ) termination for differential D December 2010 Altera Corporation ...
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Table 1–1 lists the Arria II device features. Table 1–1. Features in Arria II Devices Feature EP2AGX45 Total Transceivers (1) 8 ALMs 18,050 LEs 42,959 PCIe hard IP blocks 1 M9K Blocks 319 M144K Blocks — Total Embedded Memory in ...
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... TX, or eTX) eTX) 105(R D 85(R or eTX) D eTX) + +84(RX,TX 452 104(RX, TX, or eTX) eTX) 145(R D 85(R or eTX) D eTX) + +84(RX, TX 612 144(RX, TX, or eTX) eTX) 85(R , eTX) 145(R , eTX +84(RX, TX 612 144(RX, TX, or eTX) eTX) December 2010 Altera Corporation (8) — — ...
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... EP2AGX95 — EP2AGX125 — EP2AGX190 — EP2AGX260 — EP2AGZ225 — EP2AGZ300 — EP2AGZ350 — December 2010 Altera Corporation (Note 1152-Pin Flip Chip FBGA 35 mm × I/O LVDS (7) 135 (RX or eTX) + — 554 140 (TX or eTX) 135 (RX or eTX 554 140 (TX or eTX) ...
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... Arria II Device Architecture IV device family with a PLL Memory Interface High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL DLL Memory Interface December 2010 Altera Corporation ...
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... On-die power supply regulators for transmitter and receiver PLL charge pump ■ and voltage-controlled oscillator (VCO) for superior noise immunity Calibration circuitry for transmitter and receiver on-chip termination (OCT) ■ resistors December 2010 Altera Corporation General Purpose General Purpose PLL PLL I/O and Memory I/O and Memory ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Feature Descriptions Hard IP Data Link Layer and Transaction Layer Hard IP Data Link Layer and custom Soft IP Transaction Layer Transceiver Architecture in Arria II Devices Chapter 1: Overview for the Arria II Device Family Arria II Device Architecture chapter. December 2010 Altera Corporation ...
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... The Quartus M144K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code. December 2010 Altera Corporation ® II software allows you to take advantage of MLABs, M9K, and Arria II Device Handbook Volume 1: Device Interfaces and Integration 1– ...
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... Table 1–7. I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and RSDS 1–8. Arria II Device Architecture December 2010 Altera Corporation ...
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... MHz to support both low-cost and high-end clock performance ■ FPGA fabric can use the unused transceiver PLLs to provide more flexibility December 2010 Altera Corporation i/O Bank Bank 3C, Bank 7B, and Bank 8C Bank 3A, Bank 4A, Bank 7A, and Bank 8A ...
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... External Memory Interfaces in Arria II Devices Nios II Arria II devices support all variants of the NIOS ■ Nios II processors are supported by an array of software tools from Altera and ■ leading embedded partners and are used by more designers than any other configurable processor Configuration Features ■ ...
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... Boundary-scan test (BST) architecture offers the capability to test pin connections ■ without using physical test probes and capture functional data while a device is operating normally December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration 1–13 ...
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... Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 3 being the fastest Operating Temperature C: Commercial temperature (t = 0°C to 85° Industrial temperature (t = -40°C to 100°C) J 1–6, Table 1–7, and Table 1–9 section December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... LAB Control Block (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM MLAB LAB Logic Array Blocks December 2010 Altera Corporation ...
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... Direct link interconnect from left LAB, memory block, DSP block, or IOE output ALMs Direct link interconnect to left MLAB December 2010 Altera Corporation Local Interconnect LAB Arria II Device Handbook Volume 1: Device Interfaces and Integration 2–3 Direct link interconnect from right LAB, memory block, ...
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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Figure There are two unique clock signals per LAB. labclk0 labclk1 labclk2 labclkena0 labclkena1 labclkena2 or asyncload or labpreset Logic Array Blocks 2–4. The LAB control block syncload labclr1 labclr0 synclr December 2010 Altera Corporation ...
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... Combinational/Memory ALUT0 dataf0 datae0 6-Input LUT dataa datab datac datad 6-Input LUT datae1 dataf1 Combinational/Memory ALUT1 shared_arith_out December 2010 Altera Corporation carry_in reg_chain_in labclk adder0 D reg0 adder1 D reg1 reg_chain_out carry_out Arria II Device Handbook Volume 1: Device Interfaces and Integration 2–5 Figure 2–5 ...
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... GND + + V CC carry_out Adaptive Logic Modules CLR local D Q interconnect row, column direct link routing row, column direct link routing CLR local D Q interconnect row, column direct link routing row, column direct link routing reg_chain_out December 2010 Altera Corporation ...
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... These LAB-wide signals are available in all ALM modes. For more information on the LAB-wide control signals, refer to page 2–4. December 2010 Altera Corporation “LAB Control Signals” on Arria II Device Handbook Volume 1: Device Interfaces and Integration 2–7 ...
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... Adaptive Logic Modules 5-Input combout0 LUT 5-Input combout1 LUT 6-Input combout0 LUT 6-Input combout0 LUT 6-Input combout1 LUT December 2010 Altera Corporation ...
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... Notes to Figure 2–8: (1) If datae1 and dataf1 are used as inputs to a 6-input function, datae0 and dataf0 are available for register packing. (2) The dataf1 input is available for register packing only if the 6-input function is unregistered. December 2010 Altera Corporation (Note 1) 6-Input LUT D Q reg0 ...
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... If the 7-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Figure 2–9, often appear in designs as combout0 D Q reg0 December 2010 Altera Corporation Adaptive Logic Modules To general or local routing To general or local routing ...
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... LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. December 2010 Altera Corporation 2–10, the carry-in signal feeds to adder0 and the carry-out from carry_in ...
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... MLAB columns, the bottom half can be bypassed. 1 For more information on carry chain interconnect, refer to page 2–17. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices “ALM Interconnects” on December 2010 Altera Corporation Adaptive Logic Modules ...
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... Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or de-spread data that was transmitted using spread-spectrum technology. December 2010 Altera Corporation shows the ALM using this feature. shared_arith_in carry_in ...
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... LAB columns are bottom-half bypassable. 1 For more information on shared arithmetic chain interconnect, refer to Interconnects” on page Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices 2–17. Adaptive Logic Modules “ALM December 2010 Altera Corporation ...
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... Figure 2–13 shows the ALM in LUT-Register mode. Figure 2–13. ALM in LUT-Register Mode with 3-Register Capability clk [2..0] aclr [1..0] DC1 December 2010 Altera Corporation shows the register constructed using two combinational blocks in 4-input LUT 5-input LUT reg_chain_in Third register datain aclr ...
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... LAB labclk To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing To next ALM in the LAB “ALM Interconnects” December 2010 Altera Corporation ...
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... AC power. ■ Arria II LABs operate in high-performance mode or low-power mode. The Quartus II software automatically chooses the appropriate mode for the LAB, based on the design, to optimize speed versus leakage trade-offs. December 2010 Altera Corporation Local interconnect routing among ALMs in the LAB ALM 1 Carry chain & ...
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... Changes “Logic Array Blocks”, “LAB Interconnects”, Modules”, “ALM Operating Modes”, “Normal Mode” Figure 2–7 and Figure 2–8. “LAB Power Management Techniques” Document Revision History “LAB Control Signals”, “Adaptive sections. section. December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Outputs cleared Outputs cleared Output registers Output registers Write and Read: Rising clock edges edges December 2010 Altera Corporation ...
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... Parity Bit Support All memory blocks have built-in parity bit support. The ninth bit associated with each byte can store a parity bit or serve as an additional data bit. No parity function is actually performed on the ninth bit. December 2010 Altera Corporation MLABs Arria II GX Arria II GZ ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration ABCD ABFF FFFF XXCD ABXX ABCD ABFF FFCD ABCD Chapter 3: Memory Blocks in Arria II Devices Memory Features XXXX XX FFCD ABCD ABFF FFCD ABCD ABFF FFCD ABCD December 2010 Altera Corporation ...
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... When you configure the memory blocks in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled). December 2010 Altera Corporation ABCD ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration 1 address[0] address[0] 0 register 1 address[N] register address[N] 0 addressstall clock doutn dout0 dout1 dout0 dout1 Chapter 3: Memory Blocks in Arria II Devices Memory Features address[0] address[ dout4 dout4 dout5 December 2010 Altera Corporation ...
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... MLABs. Figure 3–6. Address Clock Enable During Write Cycle Waveform for MLABs inclock a0 wraddress data 00 wren addressstall latched address an (inside memory) contents contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 December 2010 Altera Corporation ...
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... When unregistered, it cannot be asynchronously cleared. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 3: Memory Blocks in Arria II Devices Memory Features “Memory Modes” on Figure 3–7 shows a Guide. December 2010 Altera Corporation ...
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... You cannot use the byte enable feature when ECC is engaged. 1 Read-during-write old data mode is not supported when ECC is engaged. Figure 3–8 shows a diagram of the ECC block of the M144K block. Figure 3–8. ECC Block Diagram of the M144K Block 64 64 SECDED Data Input Encoder 64 December 2010 Altera Corporation eccstatus[ ...
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... Mode Support” on page Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 3: Memory Blocks in Arria II Devices 3–21. Figure 3–9 shows the single-port RAM (Note 1) data[ ] address[ ] wren byteena[] addressstall q[] inclock outclock clockena rden aclr 3–5. December 2010 Altera Corporation Memory Modes ...
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... M144K block outputs delay the q output by one clock cycle. Figure 3–10. Timing Waveform for Read-Write Operations for M9K and M144K Blocks (Single-Port Mode) clk_a wrena rdena address_a data_a A q_a (asynch) December 2010 Altera Corporation Port Width Configurations M9K Blocks 8K × × × × × 9 512 × 16 512 × ...
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... Only available for Arria II GZ devices. Arria II Device Handbook Volume 1: Device Interfaces and Integration (old data) (old data) data[ ] wraddress[ ] wren byteena[] rd_addressstall wr_addressstall wrclock wrclocken ecc_status (1) aclr Chapter 3: Memory Blocks in Arria II Devices Memory Modes ) rdaddress[ ] rden q[ ] rdclock rdclocken December 2010 Altera Corporation ...
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... MLABs only support a write-enable signal. Read-during-write behavior for the MLABs can be either a “don’t care” or “old data” value. The available choices depend on the configuration of the MLAB. December 2010 Altera Corporation lists the mixed width configurations for the M9K blocks in simple Write Port 2K × ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration doutn dout0 dout0 doutn Chapter 3: Memory Blocks in Arria II Devices Memory Modes din4 din5 din6 din4 din5 din6 b2 b3 December 2010 Altera Corporation ...
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... M144K: 4K × 32-bit (or 4K × 36-bit with parity) Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers. December 2010 Altera Corporation ...
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... Memory Modes 512 × × 9 512 × — — v — — v — — v — — v — — — — 16K × × × 36 — — — — — — — — — December 2010 Altera Corporation ...
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... The size of a shift register (w × m × determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. December 2010 Altera Corporation ...
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... For more information about implementing FIFO buffers, refer to the DCFIFO Megafunctions User 1 MLABs do not support mixed-width FIFO mode. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 3: Memory Blocks in Arria II Devices Guide. December 2010 Altera Corporation Memory Modes n Number of Taps SCFIFO and ...
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... Similarly, a read clock controls the data-output, read-address, and read-enable registers. The memory blocks support independent clock enables for both the read and write clocks. Asynchronous clears are available on data output latches and registers only. December 2010 Altera Corporation Simple Dual-Port Mode Single-Port Mode — ...
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... Therefore, you must implement conflict resolution logic, external to the memory block, to avoid address conflicts. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 3: Memory Blocks in Arria II Devices Design Considerations Logic Array Blocks and chapter. December 2010 Altera Corporation ...
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... Figure 3–20. MLABs Blocks Same Port Read-During Write: Don’t Care Mode clk_a address XX data_in XX wrena q(unregistered) XX A0(old data) q(registered) XX December 2010 Altera Corporation Figure 3–19 shows the difference between the same port Port B data in Port B data out A0 A1 FFFF AAAA FFFF ...
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... A123 B456 C789 DDDD XX23 B4XX XXXX DDDD A123 B456 C789 DDDD B423 A0 (old data) A1(old data) old old Chapter 3: Memory Blocks in Arria II Devices Design Considerations 0B 11 EEEE FFFF EEEE FFFF A1 11 EEEE FFFF DDDD EEEE December 2010 Altera Corporation ...
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... MLABs. Figure 3–24. MLABs Mixed-Port Read-During-Write: Don’t Care Mode clk_a wraddress rdaddress AAAA data_in wrena byteena_a q_b(registered) December 2010 Altera Corporation A0 A0 BBBB CCCC DDDD AAAA AABB A0 (old data) ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration A0 AAAA BBBB CCCC DDDD AAAA AABB A0 (old data) A1(old data) A0 AAAA BBBB CCCC DDDD XXXX (unknown data) Chapter 3: Memory Blocks in Arria II Devices Design Considerations A1 EEEE FFFF 11 A1 DDDD EEEE A1 EEEE FFFF 11 A1 December 2010 Altera Corporation ...
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... The Quartus II software automatically places any unused memory block in low power mode to reduce static power. December 2010 Altera Corporation Internal Memory (RAM and ROM) and the Quartus II Handbook. ...
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... Figure 3–10, Figure 3–12, and Figure 3–16. Table 3–6 and Table 3–8. Figure 3–10, Figure 3–15, Figure 3–21, Figure “Error Correction Code Support” section. Chapter 3: Memory Blocks in Arria II Devices Document Revision History 3–23, and Figure 3–24. December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Rich and flexible arithmetic rounding and saturation units Efficient barrel shifter support ■ Loopback capability to support adaptive filtering ■ Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 4: DSP Blocks in Arria II Devices DSP Block Overview December 2010 Altera Corporation ...
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... Figure 4–1. Overview of DSP Block Signals 34 Control 144 288 Input Data 144 December 2010 Altera Corporation (Note 1) Independent Input and Output Multiplication Operators 9 × × × 18 Multipliers Multipliers Complex 232 174 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration [17..0] × B [17..0] ± A [17..0] × +/- Figure 4–2 is useful for building more complex structures, 4–8. Equation 4–1 [36.. [36.. Chapter 4: DSP Blocks in Arria II Devices Simplified DSP Operation Equation 4–1 [17..0] 1 P[36..0] and Equation 4–2 per half December 2010 Altera Corporation ...
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... The 44-bit result is either fed to the next half block or out of the DSP block with the output register stage shown in Figure December 2010 Altera Corporation [43..0] ± Z [37..0] n-1 n provides a sum of four 18 × ...
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... DSP blocks can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 4: DSP Blocks in Arria II Devices Simplified DSP Operation From Previous Half-DSP Block Next Half-DSP Block December 2010 Altera Corporation Result[] ...
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... This increases DSP block resource efficiency and allows you to implement more multipliers in an Arria II device. The Quartus II software automatically places multipliers that can share the same DSP block resources in the same block. December 2010 Altera Corporation # per Signed or RND, ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration lists the DSP block dynamic signals. zero_loopback accum_sload zero_chainout chainout_round signa signb chainout_saturate output_round output_saturate rotate shift_right (3) Chapter 4: DSP Blocks in Arria II Devices DSP Block Resource Descriptions overflow (1) chainout_sat_overflow (2) result[ ] chainout December 2010 Altera Corporation ...
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... Note to Figure 4–6: (1) The scanina signal originates from the previous DSP block, while the scanouta signal goes to the next DSP block. December 2010 Altera Corporation (Note 1) clock[3..0] ena[3..0] signa aclr[3..0] signb +/- +/- Delay Register scanouta Arria II Device Handbook Volume 1: Device Interfaces and Integration 4– ...
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... Figure 4–5 on page “Two-Multiplier Adder Sum Mode” × × × — — v — — Figure 4–14 on page 4–21. Chapter 4: DSP Blocks in Arria II Devices DSP Block Resource Descriptions 4–8. In loopback mode, the 36 × 36 Double v v — — — — December 2010 Altera Corporation ...
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... Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, rounding and saturation unit, or the output registers. December 2010 Altera Corporation 4–14. Depending on the data width of the Data B (signb Value) Unsigned (logic 0) ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 4: DSP Blocks in Arria II Devices shows that the output from the first-stage adder can either “Arria II Operational Mode Descriptions” on page DSP Block Resource Descriptions 4–14. December 2010 Altera Corporation ...
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... The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The clock[3..0], ena[3..0], and aclr[3..0] DSP block signals control the output registers in the DSP block. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration 4–13 ...
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... Figure 4–9 show the DSP block in the independent Table 4–9 on page 4–30 signa signb output_round output_saturate Half-DSP Block Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions lists the DSP block dynamic overflow (1) 36 result_0 result_1[ ] December 2010 Altera Corporation ...
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... Figure 4–8. 12-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] 12 dataa_0[11..0] 12 datab_0[11..0] 12 dataa_1[11..0] 12 datab_1[11..0] 12 dataa_2[11..0] 12 datab_2[11..0] December 2010 Altera Corporation signa signb Half-DSP Block Arria II Device Handbook Volume 1: Device Interfaces and Integration 4–15 24 result_0 result_1 result_2[ ] ...
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... DSP block. 1 The rounding and saturation logic unit is supported for 18-bit independent multiplier mode only. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions signa signb December 2010 Altera Corporation result_0[ ] result_1[ ] result_2[ ] result_3[ ] ...
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... Figure 4–10. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block December 2010 Altera Corporation signa signb + + + Arria II Device Handbook Volume 1: Device Interfaces and Integration 4–17 Figure 4–10. 72 result[ ] ...
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... Figure 4–11. Double Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Arria II Device Handbook Volume 1: Device Interfaces and Integration signa signb + + Half-DSP Block Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions Figure 4– result[ ] December 2010 Altera Corporation ...
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... December 2010 Altera Corporation signa signb Two Multiplier Adder Mode 36 + Double Mode 55 36 × 36 Mode 72 Unsigned 54 × 54 Multiplier Arria II Device Handbook Volume 1: Device Interfaces and Integration 4–19 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration (Note 1) signa signb output_round output_saturate + Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions overflow (2) result[ ] Figure 4–14 December 2010 Altera Corporation ...
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... Two-multiplier adder mode supports the rounding and saturation logic unit. You can use pipeline registers and output registers in the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. December 2010 Altera Corporation signa signb output_round output_saturate ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration shows how you can write a complex multiplication. signa signb - + Half-DSP Block Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions 36 (A × × D) (Real Part × × C) (Imaginary Part) December 2010 Altera Corporation ...
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... Four-multiplier adder mode supports the rounding and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. December 2010 Altera Corporation Figure and Equation 4–3 on page 4– ...
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... Block output for accumulator overflow and saturate overflow. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 4: DSP Blocks in Arria II Devices [53.. C[17..0] × D[35..0] 1 signa signb overflow ( << <<18 Arria II Operational Mode Descriptions Figure 4–17 shows the result[ ] December 2010 Altera Corporation ...
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... DSP block (accumulator feedback) to the output of the multiplier and first-stage adder. December 2010 Altera Corporation Equation 4–3 on page 4–5. signa ...
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... Two control signals, rotate and shift_right, together with the signa and signb signals, determine the shifting operation. Arria II Device Handbook Volume 1: Device Interfaces and Integration ® II processor to perform the dynamic shift and rotate operation. Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions December 2010 Altera Corporation ...
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... Example Signa Logical Shift Left Unsigned LSL[N] Logical Shift Right Unsigned LSR[32-N] Arithmetic Shift Left Signed ASL[N] Arithmetic Shift Right Signed ASR[32-N] Rotation ROT[N] Unsigned December 2010 Altera Corporation signa signb rotate shift_right + + + Signb Shift Rotate A-input Unsigned 0 0 0×AABBCCDD Unsigned ...
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... Add to Integer Result 1 0110 0 0011 0 0010 1 0100 1 1110 0 1011 1 1110 0 1100 Round-To-Nearest-Even ➱ 010111 0110 ➱ 001101 0011 ➱ 001010 0010 ➱ 001110 0100 ➱ 110111 1110 101101 ➱ 1011 110110 ➱ 1110 ➱ 110010 1100 December 2010 Altera Corporation ...
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... The functionality of the rounding logic unit is in the format of: Result = RND[ Likewise, the functionality of the saturation logic unit is in the format of: Result = SAT[ December 2010 Altera Corporation (n-1) (n- For example, for 32 bits: Symmetric SAT Result ...
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... Dynamically specifies whether the loopback value is zero. zero_loopback rotation = 1, rotation feature is enabled rotate Arria II Device Handbook Volume 1: Device Interfaces and Integration ∑ (A × B)]] Function Chapter 4: DSP Blocks in Arria II Devices Arria II Operational Mode Descriptions Table 4–9 lists the DSP Count December 2010 Altera Corporation ...
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... DSP block-wide asynchronous clear signals (active low) aclr2 aclr3 Total Count per Half- and Full-DSP Blocks Software Support for Arria II Devices Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: LPM_MULT ■ ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Changes “DSP Block Overview”, “Operational Modes Table 4–1 Figure 4–3, Figure 4–7, Figure 4–11, Figure 4–15 Chapter 4: DSP Blocks in Arria II Devices Document Revision History Overview”, “DSP Block Resource December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and logic array DPA clock outputs, PLD-transceiver interface clocks, horizontal I/O pins, and logic array 16 GCLKs + 16 RCLKs 16 GCLKs + 22 RCLKs 16 GCLKs + 64 RCLKs 16 GCLKs + 88 RCLKs Figure 5–1 on Figure 5–4 on page 5–5. December 2010 Altera Corporation ...
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... PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins. December 2010 Altera Corporation Figure 5–1 and Figure 5–2 CLK[12 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices LK[1 C 2..15 GCLK[12..15] GCLK[8..11] GCLK[4.. CLK[4..7] Figure 5–4 show CLK pins and PLLs that can drive RCLK networks in Clock Networks in Arria II Devices R2 CLK[8..11] R3 December 2010 Altera Corporation ...
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... A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and another four core signals can drive into RCLK[54..63] at any one time. December 2010 Altera Corporation CLK[12..15] RCLK[42 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices 16 GCLK 3 SCLK 26 16 (3) PCLK 22 (4) RCLK Clock Networks in Arria II Devices (Note 1) 9 Column I/O clock (5) 2 Core reference clock (6) 6 Row clock (7) December 2010 Altera Corporation ...
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... For Arria II GZ devices, corner PLL outputs only span one quadrant, they cannot generate a dual-regional clock network. December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration 5–7 ...
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... Clock Networks in Arria II Devices Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing. Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing. December 2010 Altera Corporation ...
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... GCLK[0..3] — — — GCLK[4..7] — — — GCLK[8..11] — — — GCLK[12..15] December 2010 Altera Corporation ® (PCIe ® ) through GCLK or RCLK networks. Table 5–3 list the connection between the dedicated clock input pins CLK (p/n Pins — — ...
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... December 2010 Altera Corporation 15 — — — — — — — — — — — — — — — — — — ...
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... II software automatically assigns PLL clock Arria II Device Handbook Volume 1: Device Interfaces and Integration 5–11 PLL Number — — — — — — — — — — — — — — — — — — — Pin-Out Files for Altera ...
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... PLL Number — — — — — — — — — — PLL Number — — — — — v — — — — — — — — — — December 2010 Altera Corporation ...
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... Select the clock source for the GCLK control block either statically with a setting in the Quartus II software or dynamically with an internal logic to drive the multiplexer select inputs. When selecting the clock source dynamically, you can either select two PLL outputs (such C1 combination of clock pins or PLL outputs. December 2010 Altera Corporation CLK Pin 2 ...
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... CLKSELECT[1..0]signal. For the connections between the PLL counter outputs to the clock control block, refer to Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Description through Table 5–10 on page 5–12. Figure 5–10. Table 5–12 on page 5–14. Clock Networks in Arria II Devices December 2010 Altera Corporation ...
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... When the device is in user mode, you can only set the clock select signals through a configuration file (.sof or .pof). You cannot dynamically control the clock. (2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input. December 2010 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction Figure 5–10 show the RCLK select blocks ...
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... Chapter 5: Clock Networks and PLLs in Arria II Devices PLL Counter Outputs and m Counter n (1) Static Clock Select Enable/ Disable Internal Logic IOE (3) Internal Logic Static Clock Select (2) PLL<#>_CLKOUT pin (1) ( Clock Networks in Arria II Devices (2) GCLK/ RCLK/ PLL_<#>_CLKOUT (1) December 2010 Altera Corporation ...
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... The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in your design. December 2010 Altera Corporation Figure 5–14. For Arria II GZ devices, the clock input sources to Arria II Device Handbook Volume 1: Device Interfaces and Integration ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Clock Control Block (ALTCLKCTRL) Megafunction User (1) 4 inclk0 To the clock switchover block (1) inclk1 4 (1) 4 inclk0 To the clock switchover block (1) inclk1 4 December 2010 Altera Corporation Clock Networks in Arria II Devices ...
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... Transceiver Clocking in Arria II Devices All Arria II PLLs have the same core analog structure and support features with minor differences in the features that are supported for Arria II GZ devices. December 2010 Altera Corporation Transceiver Clocking in Arria II Devices Figure 5–1 on page 5–3 through Overview for Arria II Device Family chapter ...
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... Single-ended only (3) Yes (3) Through GCLK and RCLK and dedicated path between adjacent PLLs (4) All except external feedback mode when you use differential I/Os Yes Yes (5) Down to 96.125 ps (5) Yes Yes Yes December 2010 Altera Corporation ...
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... Three single-ended I/O or three differential I/O pairs (this is only supported in ■ PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices). You can only access one differential I/O pair or one single-ended pin at a time. December 2010 Altera Corporation Lock locked Circuit 8 ÷n ...
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... I/O or one differential input Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Internal Logic clkena0 (3) clkena1 (3) PLL<#>_CLKOUT<#>p (1), (2) PLL<#>_CLKOUT<#>n (1), (2) Figure PLLs in Arria II Devices 5–17. Therefore, one counter December 2010 Altera Corporation ...
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... I/Os or one differential I/O pair. When using both pins as single-ended I/Os, one of them can be the clock output while the other pin is the external feedback input (FB) pin. Therefore, for single-ended I/O standards, the left and right PLLs only support external feedback mode. December 2010 Altera Corporation clkena4 (3) clkena2 (3) clkena3 (3) clkena5 (3) PLL_< ...
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... Regular I/O pins cannot drive the PLL clock input pins. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Left/Right C3 PLLs m(fbout) clkena0 (3) clkena1 (3) PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2) I/O Features in Arria II Devices chapter. PLLs in Arria II Devices Internal Logic December 2010 Altera Corporation ...
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... PLL clock outputs are operating at the desired phase and frequency set in the Quartus II software. 1 Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. f For more information about the PLL control signals, refer to the User Guide ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Availability in Arria II GZ Devices Top/Bottom PLLs Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes (4) No PLLs in Arria II Devices Left/Right PLLs Yes Yes Yes Yes Yes (3) Yes December 2010 Altera Corporation ...
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... If you do not assign the PLL Compensation assignment, the Quartus II software automatically selects all pins driven by the compensated output of the PLL as the compensation target. December 2010 Altera Corporation PLL Arria II Device Handbook Volume 1: Device Interfaces and Integration 5–27 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Figure 5–21. Thus, this mode ideally compensates for Data pin PLL reference clock at input pin Data at register Clock at register PLLs in Arria II Devices Figure 5–22 shows an example December 2010 Altera Corporation ...
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... Register Clock Port Dedicated PLL Clock Outputs (1) Note to Figure 5–23: (1) The external clock output can lead or lag the PLL internal clock signals. December 2010 Altera Corporation Phase Aligned Input Pin Figure 5–23 Phase Aligned Input Pin Arria II Device Handbook Volume 1: Device Interfaces and Integration 5– ...
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... Figure 5–24. ZDB Mode in PLLs for Arria II GZ Devices inclk ÷n Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices ÷C0 PFD CP/LF VCO ÷C1 fbout ÷m PLLs in Arria II Devices PLL_<#>_CLKOUT# PLL_<#>_CLKOUT# bidirectional I/O pin fbin December 2010 Altera Corporation ...
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... You must use the same I/O standard on the input clock, feedback input, and output clocks. Left and right PLLs support this mode when using single-ended I/O standards only. December 2010 Altera Corporation Phase Aligned Figure 5–26. Aligning these clocks allows you to Arria II Device Handbook Volume 1: Device Interfaces and Integration 5– ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Phase Aligned ÷C0 PFD CP/LF VCO ÷C1 ÷m (M/N). Each output port has a unique post-scale counter that in PLLs in Arria II Devices PLL_<#>_CLKOUT# PLL_<#>_CLKOUT# fbout external board fbin trace December 2010 Altera Corporation ...
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... VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings. For example and C1 = 20, the cascaded value is C0 × 800. 1 Post-scale counter cascading is set in the configuration file. You cannot accomplish post-scale counter cascading with PLL reconfiguration. December 2010 Altera Corporation VCO Output C0 C1 VCO Output C2 ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices 1 1 Φ fine VCO 8 8f VCO is 100 MHz and then f REF PLLs in Arria II Devices Equation 5–1. N 8Mf REF Φ is 800 MHz and VCO fin e December 2010 Altera Corporation ...
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... Arria II devices support dynamic phase-shifting of VCO phase taps only. The phase shift is reconfigurable any number of times and each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly. December 2010 Altera Corporation shows the coarse-resolution phase shifts are implemented by delaying C − 1 Φ ...
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... Automatic switchover with manual override—This mode combines modes 1 and 2. When clkswitch = 1, it overrides automatic clock switchover function. As long as the clkswitch signal is high, further switchover action is blocked. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices PLLs in Arria II Devices December 2010 Altera Corporation ...
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... PLL may lose lock after the switchover is completed and requires time to relock. 1 Altera recommends resetting the PLL with the areset signal to maintain the phase relationships between the PLL input and output clocks when you use clock switchover. ...
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... This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices (1) December 2010 Altera Corporation PLLs in Arria II Devices ...
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... The clkswitch signal and automatic switch only work if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available. December 2010 Altera Corporation (Note 1) Arria II Device Handbook Volume 1: Device Interfaces and Integration 5–39 ...
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... PLL. However, be aware that the low-bandwidth PLL also increases lock time. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices n Counter muxout refclk PLLs in Arria II Devices PFD fbclk Guide. December 2010 Altera Corporation ...
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... PLL output frequencies and adjust the output-clock phase dynamically. For instance, a system generating test patterns is required to generate and transmit patterns 150 MHz, depending on the requirements of the device under test. December 2010 Altera Corporation shows how the VCO frequency gradually decreases when the current Switchover Occurs Arria II Device Handbook Volume 1: Device Interfaces and Integration 5– ...
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... K counter is physically located after the VCO. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices ) delays in real time by changing the PLL output clock phase shift. CO (Note 1) LF/K/CP (3) PFD /C2 /C1 to counters PLLs in Arria II Devices VCO /m /C0 /n December 2010 Altera Corporation ...
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... PLL reconfiguration feature. Figure 5–36. PLL Reconfiguration Waveform for Arria II Devices Dn SCANDATA SCANCLK SCANCLKENA Dn_old SCANDATAOUT CONFIGUPDATE SCANDONE ARESET December 2010 Altera Corporation 1 through 5 to reconfigure the PLL any number of times. Arria II Device Handbook Volume 1: Device Interfaces and Integration 5–43 Phase Guide. D0 D0_old ...
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... High-time count = 1.5 cycles ■ Low-time count = 1.5 cycles ■ Duty cycle = (1.5/3) % high-time count and (1.5/3)% low-time count ■ Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices PLLs in Arria II Devices December 2010 Altera Corporation ...
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... The length of the scan chain varies for different Arria II GZ PLLs. The top and bottom PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right PLLs have seven post-scale counters and a 180-bit scan chain. December 2010 Altera Corporation Table 5–15 Block Name ...
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... The MSB for the loop filter is the last bit shifted into the scan chain. Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 5: Clock Networks and PLLs in Arria II Devices Number of Bits Counter ( — PLLs in Arria II Devices Total Other ( — 234 December 2010 Altera Corporation ...
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... Left and right PLLs have the same scan chain order. The post-scale counters end at C6. Figure 5–39 shows the scan chain bit-order sequence for post-scale counters in all Arria II PLLs. Figure 5–39. Scan Chain Bit-Order Sequence for Post-Scale Counters in Arria II PLLs DATAOUT 0 1 December 2010 Altera Corporation LSB LSB ...
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... Chapter 5: Clock Networks and PLLs in Arria II Devices Table 5–17 through Table 5–19 CP[1] CP[ LFR[3] LFR[2] LFR[1] LFR[ LFC[ PLLs in Arria II Devices show the possible settings for Decimal Value for Setting Decimal Value for Setting Decimal Value for Setting December 2010 Altera Corporation ...
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... C counters. This signal is registered in the PLL on the rising edge of scanclk. Selects dynamic phase shift direction UP DOWN. Signal is registered in the PHASEUPDOWN PLL on the rising edge of scanclk. Logic high enables dynamic phase shifting. PHASESTEP December 2010 Altera Corporation PLL Scan Chain Bits [0..8] Settings MSB (3) ...
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... I/O pin circuit PLL Logic array or I/O reconfiguration pins circuit (Note 1) [0] Selects 0 All Output Counters 1 M Counter 0 C0 Counter 1 C1 Counter 0 C2 Counter 1 C3 Counter 0 C4 Counter 1 C5 Counter 0 C6 Counter 1 C7 Counter 0 C8 Counter 1 C9 Counter December 2010 Altera Corporation ...
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... Depending on the VCO and SCANCLK frequencies, phasedone low time (t may be greater than or less than one SCANCLK cycle. f For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager interface, refer to the Megafunction User December 2010 Altera Corporation requirements with respect to the SCANCLK edges. Figure 5–40), the values of PHASEUPDOWN and b c ...
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... Table 5–7, Table 5–9, Table 5–11, “Clock Sources Per Quadrant” and “External Feedback Mode” Document Revision History Device Datasheet for Table 5–21. 5–5, Figure 5–7, Figure 5–15, Figure 5–24, Figure 5–26, andTable 5–16. sections. December 2010 Altera Corporation ...
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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. December 2010 Altera Corporation Section II. I/O Interfaces for Arria II ® II device I/O features, external memory ...
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... II–2 Arria II Device Handbook Volume 1: Device Interfaces and Integration Section II: I/O Interfaces for Arria II Devices Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... CCPD December 2010 Altera Corporation ...
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... Class II Differential HSTL-18 JESD8-6 Class I, II Differential HSTL-15 JESD8-6 Class I Differential HSTL-15 JESD8-6 Class II Differential HSTL-12 JESD8-16A Class I Differential HSTL-12 JESD8-16A Class II December 2010 Altera Corporation , and board V CCIO CCPD R EF (Note 1) (Part (V) CCIO Input Operation Output Operation Column Row I/O ...
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... Voltage) 2.5 2.5 — — 2.5 2.5 — — 2.5 2.5 — — — 2.5 — — . Row I/O banks support both true differential input “3.3-V I/O Interface” on page 6–13. when configured CCCLKIN Guide. Arria II Devices December 2010 Altera Corporation ...
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... graphical representation only. (7) The PLL_CLKOUT pin supports only emulated differential I/O standard but not true differential I/O standard. December 2010 Altera Corporation (Note 1), (2), (3), (4), (5), (6), ...
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... Each I/O bank (8) Bank 7B Bank 7A I/O banks 7A, 7B & 7C support all single-ended and differential input and output operation. I/O banks 4A, 4B & 4C support all single-ended and differential input and output operation. Bank 4B Bank 4A OCT support. when configured as CCIO December 2010 Altera Corporation ...
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... The number of I/O pins include all general purpose I/Os, dedicated clock pins, and dual-purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the I/O pin count. December 2010 Altera Corporation Table 6–4 show the number of I/O pins available in each I/O bank. ...
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Table 6–4. Available I/O Pins in Each Arria II GZ I/O Bank Bank Package Device EP2AGZ300 — 1 — 780-pin Flip Chip FBGA EP2AGZ350 — 1 — EP2AGZ225 46 42 — 1152-pin Flip EP2AGZ300 46 42 — ...
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... Each transceiver channel consists of two transmit (Tx) pins, two receive (Rx) pins and a transceiver clock pin. Table 6–6. Pin Migration Across Densities in Arria II GZ Devices Package 780-pin Flip Chip FBGA December 2010 Altera Corporation Table 6–5 (Note 1) Device EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 144 — ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Pin Type EP2AGZ225 I/O 550 Clock 4 XVCR channel 16 I/O 726 Clock 8 XVCR channel 24 Chapter 6: I/O Features in Arria II Devices I/O Structure (Note 1) (Part Device EP2AGZ300 EP2AGZ350 550 550 726 726 December 2010 Altera Corporation ...
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... Core To Core Input Pin Delay to internal Cells Read Data Synchronization to Registers Core DQS CQn DQS Bus clkin Input Register Delay December 2010 Altera Corporation OE Register PRN Q D Output Enable Pin Delay OE Register PRN D Q Programmable Current Output Register Strength and PRN ...
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... External Memory Interfaces in Arria II Devices Chapter 6: I/O Features in Arria II Devices I/O Structure DQS Logic Block D5_OCT D6_OCT Dynamic OCT Control (2) V CCIO V CCIO PCI Clamp Programmable Pull-Up Resistor From OCT Calibration Block Output Buffer On-Chip Termination Input Buffer Bus-Hold Circuit chapter. December 2010 Altera Corporation ...
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... CCIO for Arria II GZ devices. To ensure device reliability and proper operation when interfacing a 3.3-V I/O system with Arria II devices, do not exceed the absolute maximum ratings. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are within the guidelines. ...
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... Top, Bottom, and Right I/O Pins (2) Chapter 6: I/O Features in Arria II Devices I/O Structure High-Speed Differential I/O and Table 6–8 list the (Note Current Strength Setting (mA) OH [12 [2] 16, 12 16, 12 16, 12 16, 12, 10 16, 12, 10 12 12, 10, 8 16, 12 12, 10, 8 12, 10 12, 10 December 2010 Altera Corporation ...
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... HSTL and SSTL Class I I/O standards. The default setting is 25- Class II I/O standards. (2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using V 1 Altera recommends performing IBIS or SPICE simulations to determine the right current strength setting for your specific application. December 2010 Altera Corporation I ...
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... You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. 1 Altera recommends performing IBIS or SPICE simulations to determine the right slew rate setting for your specific application. Open-Drain Output Arria II devices provide an optional open-drain output (equivalent to an open collector output) for each I/O pin ...
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... A higher V while a smaller V f For more information about programmable V Interfaces with DPA in the Arria II Devices December 2010 Altera Corporation chapter. level. CCIO swing improves voltage margins at the receiver end, OD swing reduces power consumption ...
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... V. The LVDS input operations are supported when V CCIO output operations are only supported when V (3) Altera recommends using an external clamp diode on the column I/O pins when the input signal is 3 3.3 V. (4) Not applicable for Arria II GZ devices. Arria II Device Handbook Volume 1: Device Interfaces and Integration Table 6– ...
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... As a result, you can significantly reduce reflections. Arria II devices support R OCT for single-ended I/O standards. S December 2010 Altera Corporation OCT Control for Arria II GZ Devices” S OCT with Calibration for Arria II GZ Devices” S and R OCT for Single-Ended I/O Standard for Arria II GZ Devices” ...
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... OCT with calibration in all banks. The R S Figure 6–6 is the intrinsic impedance of transistors. Calibration OCT with Calibration for Arria II Devices Arria II Driver Series Termination V CCIO GND Chapter 6: I/O Features in Arria II Devices OCT Support Receiving Device ). TT OCT calibration S Receiving Device December 2010 Altera Corporation ...
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... CCIO R OCT for SSTL-2 Class I and Class II I/O standards, you only need one OCT S calibration block with 50-Ω external reference resistors. December 2010 Altera Corporation OCT Selectable I/O Standards With and Without Calibration for Arria II Devices R OCT Termination Setting S Row I/O (Ω) ...
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... OCT with 50-Ω external S OCT. S OCT values S OCT S OCT calibration settings of 25, 40, 50, OCT with calibration settings S OCT with Calibration Range for Arria OCT Range S Column I/O (Ω) 20–60 20–60 20–60 20–60 20–60 20–60 20–60 20–60 20–60 20–60 20–60 December 2010 Altera Corporation ...
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... Output pin configurations do not support R R OCT with calibration. When you use R T I/O standard of the pin where the R Figure 6– December 2010 Altera Corporation Figure 6–7. However, not all input differential pins OCT when both the V D OCT. You can enable the Arria and V is set to 2 ...
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... OCT Setting T (Column I/O) (Ω and R OCT for Single-Ended I/O Standard for Arria II GZ Devices T Figure 6–9 Chapter 6: I/O Features in Arria II Devices OCT Support Table 6–13 lists the R OCT Setting T (Row I/O) (Ω shows the termination schemes December 2010 Altera Corporation ...
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... Arria II GZ OCT VCCIO 100 50 50 100 GND Receiver Arria II GZ OCT f For more information about tolerance specifications for OCT with calibration, refer to the Arria II Device Data Sheet December 2010 Altera Corporation VCCIO 100 100 GND Arria II GZ OCT VCCIO 100 100 Z ...
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... Chapter 6: I/O Features in Arria II Devices Arria II OCT Calibration of the I/O bank CCIO of the I/O bank with the CCIO and Arria II Device voltage CCIO CCIO voltage, you can use one OCT CCIO as bank 7A, you can calibrate CCIO OCT calibration codes from S December 2010 Altera Corporation ...
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... Arria II GZ Devices Bank 1A Bank 1C Bank 2C Bank 2A f For more information about the OCT calibration block, refer to the Megafunction User December 2010 Altera Corporation Bank 6A Bank 6C Arria II GZ Device Bank 5C Bank 5A Guide. Arria II Device Handbook Volume 1: Device Interfaces and Integration 6–27 ...
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... Series OCT 50 Receiver Transmitter Chapter 6: I/O Features in Arria II Devices Termination Schemes for I/O Standards ) and SSTL Class REF Receiver REF Receiver CCIO Parallel OCT 50 100 REF 100 Receiver V CCIO 100 50 100 Series OCT 25 Receiver December 2010 Altera Corporation ...
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... Receive (1) V REF Transmitter V CCIO Series OCT OCT 50 100 in Bi- Directional 50 Pins (1) 100 Transmitter Note to Figure 6–12: (1) Applicable to Arria II GZ devices only. December 2010 Altera Corporation REF Transmitter Receiver V TT Series OCT 25 Transmitter Receiver V CCIO Parallel OCT 100 100 Transmitter Receiver V CCIO ...
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... Termination Schemes for I/O Standards Figure 6–13 through Differential SSTL Class Ω 50 Ω 50 Ω 50 Ω 25 Ω 50 Ω 25 Ω 50 Ω Receiver Ω 50 Ω Ω Ω 50 Ω Ω Receiver V TT Parallel OCT V CCIO 100 50 100 100 CCIO GND 50 100 100 GND Receiver December 2010 Altera Corporation ...
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... Differential HSTL Class I 50 Ω Series OCT OCT and S R OCT for T Arria II GZ Devices Transmitter December 2010 Altera Corporation 50 Ω Receiver Transmitter HSTL Class Series OCT 50 Ω Ω Receiver Transmitter Differential HSTL Class II 25 Ω Parallel OCT Series OCT V CCIO ...
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... For LVDS output with a one-resistor network, and Chapter 6: I/O Features in Arria II Devices Termination Schemes for I/O Standards . LVDS requires a CCPD Differential Inputs 100 Ω Differential Inputs 100 Ω Arria II OCT Differential Inputs 100 Ω Arria II OCT Differential Inputs 100 Ω Arria II OCT December 2010 Altera Corporation ...
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... Arria II devices supports true RSDS, RSDS with a one-resistor network, and RSDS with a three-resistor network. Two single-ended output buffers are used for external one- or three-resistor networks, as shown in banks support RSDS output using true LVDS output buffers without an external resistor network. December 2010 Altera Corporation 0.1 μ ...
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... The resistor values chosen should satisfy the equation shown in Equation 6–1. Resistor Network 1 To validate that custom resistor values meet the RSDS requirements, Altera recommends performing additional simulations with IBIS models. f For more information about the RSDS I/O standard, refer to the RSDS Specification from the National Semiconductor website at www ...
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... The termination resistor must match the differential load impedance of the signal line. Arria II devices provide an optional differential on-chip resistor when you use LVDS. December 2010 Altera Corporation ). The reference voltage of the receiving device tracks the TT OCT impedance to match the ...
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... I/O bank to match the voltage of the CCIO . CCIO Chapter 6: I/O Features in Arria II Devices Design Considerations . An CCIO 6–2. CCIO or GND. Each bank can only CCIO voltage level at a given time. level CCPD CCIO and a 0.9 CCIO REF and 0.75 CCIO REF December 2010 Altera Corporation ...
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... Arria II devices and includes essential information for designing systems with an Arria II device’s selectable I/O capabilities. 3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O standards to limit overshoot and undershoot at I/O pins: ■ ...
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... Devices”, “R OCT with Calibration for Arria and R OCT for Single-Ended I/O Standard for Arria II GZ Devices” Figure 6–1. Chapter 6: I/O Features in Arria II Devices Document Revision History Devices”, “Expanded R OCT with S Devices”, and sections. December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Control Postamble Clock Circuit 2n 2n Synchronization Registers ( (Note 1) , (2) Memory DQS Logic DQS (Read) (4) Block DQS Enable Circuit DDR Input n Registers DQ (Read) ( (Write) (4) DDR Output and Output Enable Registers DQS (Write) (4) DDR Output and Output Enable Registers December 2010 Altera Corporation ...
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... Arria II DDR I/O registers (DDIOs) to ensure that timing relationships between the CK/CK# and DQS signals (t DDR2, and DDR SDRAM devices) are met. The QDR II+/QDR II SRAM devices use the same clock (K/K#) to capture the write data, address, and command signals. December 2010 Altera Corporation DLL Postamble Enable Postamble ...
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... Section I. Device and Pin Planning in volume 2 of the External Memory Figure 7–3), marked in the pin table with DIFFIN or (Note 1) FPGA LEs I/O Elements voltage is provided to that I/O bank’s VREF pins. REF Memory Interfaces Pin Support for Arria II Devices mem_clk (2) mem_clk_n (2) December 2010 Altera Corporation ...