EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 117

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
December 2010 Altera Corporation
Clock Control Block
Every GCLK and RCLK network has its own clock control block. The control block
provides the following features:
■
■
■
Figure 5–8
Figure 5–8. GCLK Control Block for Arria II Devices
Notes to
(1) You can only dynamically control these clock select signals through internal logic when the device is operating in user
(2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
(3) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the
(4) This is only available on the left side of the Arria II GX device.
Select the clock source for the GCLK control block either statically with a setting in the
Quartus II software or dynamically with an internal logic to drive the multiplexer
select inputs. When selecting the clock source dynamically, you can either select two
PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
Clock source selection (dynamic selection for GCLKs)
GCLK multiplexing
Clock power down (static or dynamic clock enable or disable)
mode.
controlled during user mode operation.
GCLK network.
Figure
shows the GCLK select blocks for Arria II devices.
5–8:
CLKSELECT[1..0]
PLL Counter
Outputs (3)
This multiplexer
supports user-controllable
dynamic switching
(1)
2
Arria II Device Handbook Volume 1: Device Interfaces and Integration
2
CLK
Pin
2
Enable/
Disable
GCLK
CLK
Pin
Block Clock Lines
Inter-Transceiver
Static Clock
Internal
Select (2)
Logic
Internal
(4)
Logic
5–13