EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 458

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–72
Table 1–20. SDI Mode Data Rates, refclk Frequencies, and Interface Widths in Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
Configuration Data Rate (Mbps)
HD
SDI
f
f
1
1483.5
The following is the time taken by a PCIe port, implemented in an Arria II GX or GZ
device, to go from the power-up to the link-active state:
■
■
■
To meet the PCIe specification of 200 ms from the power-on to the link-active state, the
Arria II GX and GZ device configuration time must be less than 148 ms (200 ms to 12
ms for power on reset, 40 ms for the link to become active after PERST# de-assertion).
For the typical Arria II GX and GZ configuration times using the Fast Passive Parallel
(FPP) configuration scheme at 125 MHz, refer to the
Devices.
For more information about the FPP configuration scheme, refer to the
Design Security, Remote System Upgrades in Arria II Devices
Most flash memories available in the market can run up to 100 MHz. Altera
recommends using a MAX II device to convert the 16-bit flash memory output at
62.5 MHz to 8-bit configuration data input to the Arria II GX and GZ devices at
125 MHz.
The Society of Motion Picture and Television Engineers (SMPTE) defines various SDI
standards for the transmission of uncompressed video.
The following three SMPTE standards are popular in video broadcasting applications:
■
■
■
Table 1–20
Arria II GX and GZ transceivers in SDI mode.
1485
Power-on reset—begins after power rails become stable, which typically takes
12 ms
FPGA configuration and programming—begins after power on reset.
Configuration time depends on the FPGA density
Time taken from de-assertion of PERST# to link active—typically takes 40 ms
(pending characterization and verification of the PCIe soft IP and hard IP)
SMPTE 259M standard, more popularly known as the standard-definition (SD)
SDI—is defined to carry video data at 270 Mbps.
SMPTE 292M standard, more popularly known as the high-definition (HD)
SDI—is defined to carry video data at 1485 Mbps or 1483.5 Mbps.
SMPTE 424M standard, more popularly known as the third-generation (3G)
SDI—is defined to carry video data at 2970 Mbps or 2967 Mbps.
lists the data rates, refclk frequencies, and interface widths supported by
Frequencies (MHz)
Support refclk
74.175
148.35
74.25
148.5
FPGA Fabric-to-Transceiver
Width
20-bit
10-bit
20-bit
10-bit
Chapter 1: Transceiver Architecture in Arria II Devices
Device Datasheet for Arria II
chapter.
December 2010 Altera Corporation
Byte Serializer/Deserializer
Not used
Not used
Usage
Used
Used
Configuration,
Functional Modes