EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 365

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
I/O Voltage Support in a JTAG Chain
I/O Voltage Support in a JTAG Chain
Table 11–3. Supported TDO/TDI Voltage Combinations for Arria II GX Devices (Part 1 of 2)
December 2010 Altera Corporation
Arria II GX
Device
EXTEST_TRAIN Instruction Mode
1
1
TDI Input Buffer
The instruction code for EXTEST_TRAIN is 0001001111. The EXTEST_TRAIN instruction
behaves like the EXTEST_PULSE instruction with one exception: the output continues to
toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE
state.
These two instruction codes are only supported in post-configuration mode for
Arria II GX devices.
You must not use the following private instructions as invoking such instructions
potentially damage the device, rendering the device useless:
You must take precaution not to invoke such instructions at any instance. Altera
recommends that you avoid toggling the JTAG pins when the device is not in used.
The JTAG chain can support several different devices. However, use caution if the
chain contains devices that have different V
TDO pin must meet the specification of the TDI pin it drives.
Table 11–3
JTAG chain operation.
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
■
■
■
■
■
■
Power
= 3.3 V
= 3.0 V
= 2.5 V
= 1.8 V
= 1.5 V
1100010000
0011100101
0011001001
1100010011
0011100110
0000101010
and
Table 11–4
V
CCIO
= 3.3 V
v
v
v
v
v
show board design recommendations to ensure proper
(1)
Arria II GX TDO V
V
CCIO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
= 3.0 V
v
v
v
v
v
CCIO
(1)
CCIO
levels. The output voltage level of the
V
CCIO
Voltage Level in I/O Bank 8C
= 2.5 V
v
v
v
v
v
(2)
V
CCIO
v
v
v
v
v
= 1.8 V
(3)
(3)
(3)
(3)
(3)
V
Level shifter
Level shifter
Level shifter
Level shifter
CCIO
required
required
required
required
11–5
v
= 1.5 V