EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 562

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–4
Arria II Device Handbook Volume 2: Transceivers
1
Table 3–1. Configuration for Example 1 for Arria II Devices (Part 2 of 2)
You can share a single CMU PLL for all four channels:
■
■
The following steps describe how to achieve the configuration.
To enable the Quartus II software to share a single CMU PLL for all four channels, set
the following values in the General screen of the ALTGX MegaWizard Plug-In
Manager.
■
■
■
■
The Specify base data rate option is 3.75 Gbps for all four instances. Because the
CMU PLL bandwidth setting and input reference clock are the same and the
pll_powerdown ports are driven from the same logic or pin, the Quartus II software
shares a single CMU PLL that runs at 3.75 Gbps.
You can force the placement of transceiver channels to a specific transceiver block by
assigning pins to tx_dataout and rx_datain. Otherwise, the Quartus II software
selects a transceiver block.
Figure 3–1
transceiver channel instances. Because the RX CDR is not shared between channels,
only the CMU PLL is shown.
User-Created
Instance Name
inst2
inst3
One CMU PLL can be configured to run at 3.75 Gbps.
Each channel can divide the CMU PLL clock output using the local divider and
achieve the required data rates of 3.75 Gbps, 1.875 Gbps, and 0.9375 Gbps. Because
each receiver channel has a dedicated CDR, the receiver side in each instance can
be set up for these three data rates without restrictions.
For inst0:
■
■
For inst1:
■
■
For inst2:
■
■
For inst3:
■
■
Set What is the effective data rate? to 3.75 Gbps
Set Specify base data rate to 3.75 Gbps
Set What is the effective data rate? to 1.875 Gbps
Set Specify base data rate to 3.75 Gbps
Set What is the effective data rate? to 0.9375 Gbps
Set Specify base data rate to 3.75 Gbps
Set What is the effective data rate? to 3.75 Gbps
Set Specify base data rate to 3.75 Gbps
shows the scenario before and after the Quartus II software combines the
Number of Channels
1
1
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
ALTGX MegaWizard Plug-In Manager Settings
Receiver and Transmitter
Receiver and Transmitter
Configuration
December 2010 Altera Corporation
Effective Data Rate
(Gbps)
1.875
Sharing CMU PLLs
3.75