EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 424

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–38
Table 1–12. Word Aligner Options Available in Basic Single-Width and Double-Width Modes for Arria II
Devices
Arria II Device Handbook Volume 2: Transceivers
Basic
Single-Width
Functional
Mode
(Note 1)
PMA-PCS
(Part 1 of 2)
Interface
Width
10-bit
8-bit
Table 1–12
double-width modes.
Word Alignment
Synchronization
State Machine
Alignment
Alignment
Automatic
Manual
Bit-Slip
Manual
Bit-Slip
summarizes the word aligner options available in Basic single-width and
Mode
7- and 10-bit
7- and 10-bit
7- and 10-bit
Alignment
Pattern
Length
16-bit
16-bit
Word
rx_enapatternalign
Level Sensitive
Rising Edge
Sensitivity
Sensitive
—
—
—
Chapter 1: Transceiver Architecture in Arria II Devices
one parallel clock
one parallel clock
Asserted high for
Asserted high for
synchronization
word boundary.
word boundary.
aligns to a new
aligns to a new
rx_syncstatus
cycle when the
cycle when the
conditions are
Stays high as
word aligner
word aligner
long as the
Behavior
satisfied.
December 2010 Altera Corporation
—
—
Receiver Channel Datapath
pattern appears in
pattern appears in
pattern appears in
pattern appears in
pattern appears in
rx_patterndetect
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
the current word
the current word
the current word
the current word
the current word
word alignment
word alignment
word alignment
word alignment
word alignment
cycle when the
cycle when the
cycle when the
cycle when the
cycle when the
boundary.
boundary.
boundary.
boundary.
boundary.
Behavior