EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 35

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
December 2010 Altera Corporation
ALM Operating Modes
This feature is called register packing. It improves device utilization by allowing the
device to use the register and combinational logic for unrelated functions. Another
mechanism to improve fitting is to allow the register output to feed back into the LUT
of the same ALM so that the register is packed with its own fan-out LUT. The ALM
can also drive out registered and unregistered versions of the LUT or adder output.
The Quartus II software automatically configures the ALMs for optimized
performance.
The Arria II ALM can operate in any of the following modes:
■
■
■
■
■
The Quartus II software and other supported third-party synthesis tools, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions, automatically choose the appropriate mode for common
functions such as counters, adders, subtractors, and arithmetic functions. Each mode
uses the ALM resources differently. In each mode, eleven available inputs to an
ALM—the eight data inputs from the LAB local interconnect, carry-in from the
previous ALM or LAB, the shared arithmetic chain connection from the previous
ALM or LAB, and the register chain connection—are directed to different destinations
to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all ALM modes. For more
information on the LAB-wide control signals, refer to
page
Normal
Extended LUT
Arithmetic
Shared Arithmetic
LUT-Register
2–4.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
“LAB Control Signals” on
2–7