EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 248

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–8
Differential Transmitter
Figure 8–4. LVDS Transmitter Block Diagram
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
(3) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
Serializer
8–4:
1
tx_coreclock
Fabric
FPGA
tx_in
The Arria II transmitter has a dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and
PLLs that can be shared between the transmitter and receiver. The differential buffer
can drive out LVDS, mini-LVDS, and RSDS signaling levels. The differential output
buffer supports programmable pre-emphasis and programmable voltage output
differential (V
Figure 8–4
When using emulated LVDS I/O standards at the differential transmitter, the SERDES
circuitry must be implemented in logic cells but not hard SERDES.
The serializer takes parallel data from the FPGA fabric, clocks it into the parallel load
registers, and serializes it using the shift registers before sending the data to the
differential output buffer. The MSB of the parallel data is transmitted first. The
parallel load and shift registers are clocked by the high-speed clock running at the
serial data rate (diffioclk) and controlled by the load enable signal (LVDS_LOAD_EN)
generated from the PLL. You can statically set the serialization factor to ×4, ×6, ×7, ×8,
or ×10 using the ALTLVDS megafunction. The load enable signal is derived from the
serialization factor setting.
You can bypass the serializer to support DDR (×2) and SDR (×1) operations to achieve
a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data
output registers that can each operate in either DDR or SDR mode.
the serializer bypass path.
10
is a block diagram of the LVDS transmitter.
DIN
Serializer
OD
PLL (3)
3
) controls, and can drive out mini-LVDS and RSDS signaling levels.
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
(Note
2
1),
IOE
tx_inclock
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
(2)
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
LVDS Clock Domain
December 2010 Altera Corporation
+
-
Figure 8–5
tx_out
Differential Transmitter
shows