EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 76

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–4
Simplified DSP Operation
Figure 4–2. Basic Two-Multiplier Adder Building Block
Arria II Device Handbook Volume 1: Device Interfaces and Integration
A0[17..0]
B0[17..0]
A1[17..0]
B1[17..0]
In Arria II devices, the fundamental building block is a pair of 18 × 18-bit multipliers
followed by a first-stage 37-bit addition and subtraction unit shown in
and
2’s-complement format only.
Equation 4–1. Multiplier Equation
The structure shown in
such as complex multipliers and 36 × 36 multipliers, as described in later sections.
Each Arria II DSP block contains four two-multiplier adder units
(2 two-multiplier adder units per half block). Therefore, there are eight 18 × 18
multiplier functionalities per DSP block. For a detailed diagram of the DSP block,
refer to
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions shown in
block.
Equation 4–2. Four-Multiplier Adder Equation
Figure
Figure 4–5 on page
P[36..0] = A
Z[37..0] = P
4–2. For all signed numbers, input and output data is represented in
D
D
Q
Q
0
0
[36..0] + P
[17..0] × B
Figure 4–2
4–8.
1
0
[36..0]
[17..0] ± A
is useful for building more complex structures,
1
[17..0] × B
Equation 4–1
+/-
1
[17..0]
Chapter 4: DSP Blocks in Arria II Devices
and
December 2010 Altera Corporation
Equation 4–2
P[36..0]
Simplified DSP Operation
Equation 4–1
per half