EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 283

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Configuration Features
Table 9–2. Configuration Features for Arria II GZ Devices
December 2010 Altera Corporation
FPP
Fast AS
PS
JTAG
Notes to
(1) In these modes, the host system must send a DCLK that is ×4 the data rate.
(2) Remote system upgrade is only available in the fast AS configuration scheme. Local update mode is not supported in the fast AS configuration
Configuration
Scheme
scheme.
Table
9–2:
MAX II device or a microprocessor with flash memory
Serial configuration device
MAX II device or a microprocessor with flash memory
Download cable
MAX II device or a microprocessor with flash memory
Download cable
Table 9–2
Arria II GZ devices.
You can refer to the following for the configuration features supported in Arria II
devices:
■
■
■
■
If your system already contains a common flash interface (CFI) flash memory device,
you can also use it for the Arria II device configuration storage. The PFL feature in
MAX II devices provides an efficient method to program CFI flash memory devices
through the JTAG interface and provides the logic to control configuration from the
flash memory device to the Arria II device. Both passive serial (PS) and fast passive
parallel (FPP) configuration modes are supported using this PFL feature.
For more information about programming Altera serial configuration devices, refer to
“Programming Serial Configuration Devices” on page
For more information about the configuration data decompression feature, refer to
“Configuration Data Decompression” on page
For more information about the remote system upgrade feature, refer to
System Upgrades” on page
For more information about the design security feature, refer to the
Security” on page
For more information about the parallel flash loader (PFL), refer to
Loader Megafunction User
Configuration Method
lists the configuration features you can use in each configuration scheme for
9–61.
Guide.
9–48.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Decompression
v
v
v
v
—
—
9–46.
(1)
9–23.
Security
Design
v
v
v
v
—
—
(1)
Parallel Flash
Remote System
“Design
Upgrade
v
“Remote
—
—
—
—
—
(2)
9–3