EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 318

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–38
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Jam STAPL
f
Figure 9–18
Figure 9–18. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II devices in the chain.
(2) To drive the JTAG pins, the microprocessor must use the same I/O standard as V
(3) You must connect nCE to GND or drive it low for successful JTAG configuration.
(4) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you use only the JTAG
Jam standard test and programming language (STAPL), JEDEC standard JESD-71, is a
standard file format for in-system programmability (ISP) purposes. Jam STAPL
supports programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely
licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the Jam Player, visit the
AN 425: Using Command-Line Jam STAPL Solution for Device
The V
enough to meet the V
for Arria II GZ devices.
configuration, connect nCONFIG to the V
Pull DCLK either high or low, whichever is convenient on your board. Arria II GX devices use MSEL[3..0] pins while
Arria II GZ devices use MSEL[2..0] pins.
Figure
CCIO
power supply for Arria II GX devices or the V
shows a JTAG configuration of an Arria II device using a microprocessor.
9–18:
Microprocessor
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
IH
ADDR
specification of the I/O on the device.
Memory
DATA
CCIO
Altera
for Arria II GX device, V
TDI (2)
TCK (2)
TMS (2)
TDO (2)
website.
CCPGM
Arria II Device
CONF_DONE
power supply for Arria II GZ devices must be high
MSEL[n..0]
nSTATUS
nCONFIG
(3) nCE
DCLK
nCEO
CCPGM
V CCIO
for Arria II GZ device, and MSEL to GND.
/
(4)
(4)
(4)
N.C.
(1)
V CCPGM
GND
December 2010 Altera Corporation
V CCIO
10 kΩ
CCIO
Programming. To
for Arria II GX devices or V
/
(1)
V CCPGM
10 kΩ
JTAG Configuration
CCPD