EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 230

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–34
Figure 7–21. DQS Logic Block for Arria II Devices
Notes to
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input
(2) The dqsenable signal can also come from the Arria II GX FPGA fabric.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DQS phase-shift
settings from the
DQS phase-shift
clock pin, refer to
settings from
Phase offset
DQS delay
circuitry
circuitry
Figure
DQS Logic Block
offsetctrlin [5:0]
delayctrlin [5:0]
7–21:
6
6
<dqs_offsetctrl_enable>
DQS/CQ or
0
1
CQn Pin
Table 7–6 on page 7–28
6
Bypass
D
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which
consists of DQS delay chains, update enable circuitry, and DQS postamble circuitry
(refer to
DQS Delay Chains
DQS delay chains consist of a set of variable delay elements to allow the DQS/CQ and
CQn inout signals to be shifted by the amount specified by the DQS phase-shift
circuitry or the logic array. There are four delay elements in the DQS delay chain; the
first delay chain closest to the DQS/CQ or CQn pin can either be shifted by the DQS
delay settings or by the sum of DQS delay setting and the phase-offset setting. The
number of delay chains required is transparent because the ALTMEMPHY
megafunction and UniPHY IP core automatically set it when you choose the
operating frequency. The DQS delay settings can come from the DQS phase-shift
circuitry on either end of the I/O banks or from the logic array.
Q
Input Reference
dqsin
6
Clock (1)
0
1
6
Figure
D
DQS Delay Chain
and
Q
7–21).
dqsupdateen
6
Table 7–10 on page
0
1
6
<dqs_ctrl_latches_enable>
Update
Circuitry
Enable
7–32.
<phase_setting>
Resynchronization
Postamble
Enable
Clock
Chapter 7: External Memory Interfaces in Arria II Devices
DQS Enable
dqsin
DQS Enable Control
dqsenablein
clk
dqsbusout
Arria II External Memory Interface Features
DQS bus
D
D
Q
Q
December 2010 Altera Corporation
dqsenable (2)
<delay_dqs_enable_by_half_cycle>
Q
PRE
D
0
1
dqsenableout