EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 106

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–2
Table 5–1. Clock Resources in Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Notes to
(1) There are 64 RCLKs in the EP2AGZ225 devices. There are 88 RCLKs in the EP2AGZ300 and EP2AGZ350 devices.
(2) There are 50 PCLKs in EP2AGX45 and EP2AGX65 devices, where 18 are on the left side and 32 on the right side. There are 59 PCLKs in
(3) There are 32 GCLKs/RCLKs per quadrant in the EP2AGZ225 devices. There are 38 GCLKs/RCLKs per quadrant in the EP2AGZ300 and
(4) There are 80 GCLKs/RCLKs per entire device in the EP2AGZ225 devices. There are 104 GCLKs/RCLKS per entire device in the EP2AGZ300 and
GCLKs/RCLKs per
GCLKs/RCLKs per
Clock Resource
Clock input pins
GCLK networks
RCLK networks
PCLK networks
and Device
EP2AGX95 and EP2AGX125 device, where 27 are on the left side and 32 on the right side. There are 84 PCLKs in EP2AGX190 and EP2AGX260
devices, where 36 are on the left side and 48 on the right side.
EP2AGZ350 devices.
EP2AGZ350 devices.
quadrant
device
Table
5–1:
(6 Differential)
(24 per device
quadrant)
Single-ended
Table 5–1
Arria II GX devices have up to 12 dedicated single-ended clock pins or six dedicated
differential clock pins (DIFFCLK_[0..5]p and DIFFCLK_[0..5]n) that can drive either
the GCLK or RCLK networks. These clock pins are arranged on the three sides
(top, bottom, and right sides) of the Arria II GX device, as shown in
page 5–3
Arria II GZ devices have up to 32 dedicated single-ended clock pins or 16 dedicated
differential clock pins (CLK[0..15]p and CLK[0..15]n) that can drive either the GCLK
or RCLK networks. These clock pins are arranged on the four sides of the Arria II GZ
device, as shown in
Arria II GX
Number of Resources Available
12
16
48
84
28
64
(2)
and
lists the clock resources available in Arria II devices.
Figure 5–3 on page
32 Single-ended
(16 Differential)
(22 per device
80/104
Arria II GZ
32/38
quadrant)
64/88
Figure 5–2 on page 5–4
16
88
(1)
(3)
(4)
5–5.
programmable logic device
(PLD)-transceiver interface
DIFFCLK_[0..5]p/n pins
clocks, horizontal I/O pins,
Dynamic phase alignment
PLD-transceiver interface
PLD-transceiver interface
CLK[4..15] pins, PLL
CLK[4..15] pins, PLL
clocks, and logic array
clocks, and logic array
16 GCLKs + 12 RCLKs
16 GCLKs + 48 RCLKs
(DPA) clock outputs,
and logic array
clock outputs,
clock outputs,
CLK[4..15],
Arria II GX
and
Chapter 5: Clock Networks and PLLs in Arria II Devices
Source of Clock Resource
Figure 5–4 on page
clock outputs, and logic array
clock outputs, and logic array
December 2010 Altera Corporation
CLK[0..15]n pins, PLL
CLK[0..15]n pins, PLL
clocks, horizontal I/O pins,
PLD-transceiver interface
Clock Networks in Arria II Devices
andCLK[0..15] n pins
16 GCLKs + 16 RCLKs
16 GCLKs + 22 RCLKs
16 GCLKs + 64 RCLKs
16 GCLKs + 88 RCLKs
CLK[0..15]p and
CLK[0..15]p and
DPA clock outputs,
and logic array
CLK[0..15]p
Arria II GZ
5–5.
Figure 5–1 on