EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 233

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
December 2010 Altera Corporation
Arria II GZ Dynamic On-Chip Termination Control
I/O Element Registers
f
Figure 7–24
required to dynamically turn on the on-chip parallel termination (R
read and turn R
For more information about the dynamic OCT control block, refer to the
in Arria II Devices
Figure 7–24. Dynamic OCT Control Block for Arria II GZ Devices
Note to
(1) The write clock comes from the PLL.
IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. For Arria II GX devices, both top,
bottom, and right IOEs have the same capability. Right IOEs have extra features to
support LVDS data transfer. For Arria II GZ devices, both top and bottom, and left
and right IOEs have the same capability. Left and right IOEs have extra features to
support LVDS data transfer.
Figure
7–24:
shows the dynamic OCT control block. The block includes all the registers
T
OCT off during a write.
chapter.
OCT Control Path
Half-Rate Clock
OCT Control
OCT
2
Arria II Device Handbook Volume 1: Device Interfaces and Integration
HDR
Block
DFF
Write Clock (1)
Resynchronization
Registers
DFF
OCT Enable
T
OCT) during a
I/O Features
7–37