EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 110

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–6
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Periphery Clock Networks
Clock Sources Per Quadrant
1
PCLK networks are a collection of individual clock networks driven from the
periphery of the Arria II device. Clock outputs from the DPA block, PLD-transceiver
interface clocks, horizontal I/O pins, and internal logic can drive the PCLK networks.
The number of PCLKs for each Arria II device are as follows:
■
■
■
■
PCLKs have higher skew when compared with the GCLK and RCLK networks. You
can use PCLKs instead of general purpose routing to drive signals into the Arria II
device.
The legal clock sources for PCLK networks are clock outputs from the DPA block,
PLD-transceiver interface clocks, horizontal I/O pins, and internal logic.
There are 26 section clock (SCLK) networks available in each spine clock that can
drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and
three core reference clocks. The SCLKs are the clock resources to the core functional
blocks, PLLs, and I/O interfaces of the device.
Figure 5–5
each spine clock can drive the SCLKs.
Figure 5–5. Hierarchical Clock Networks per Spine Clock in Arria II Devices
Notes to
(1) The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. The total number of clock
(2) There are up to three PLL feedback clock which are from the PLL that drives into the SCLKs.
(3) There are up to 16 PCLKs that can drive the SCLKs in each spine clock in the largest device.
(4) There are up to 22 RCLKs (Arria II GZ), 12 RCLKs (Arria II GX) that can drive the SCLKs in each spine clock in the
(5) The column I/O clock drives the column I/O core registers and I/O interfaces.
(6) The core reference clock feeds into the PLL as the PLL reference clock.
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row.
EP2AGX45 and EP2AGX65 devices contain 50 PCLKs
EP2AGX95 and EP2AGX125 devices contain 59 PCLKs
EP2AGX190 and EP2AGX260 devices contain 84 PCLKs
EP2AGZ225, EP2AGZ300, and EP2AGZ350 devices contain 88 PCLKs
resources must not exceed the SCLK limits in each region to ensure successful design fitting in the Quartus II
software.
largest device.
PLL feedback clock (2)
Figure
shows that the GCLK, RCLK, PCLK, or the PLL feedback clock networks in
5–5:
GCLK
PCLK
RCLK
16
16 (3)
22 (4)
3
SCLK
Chapter 5: Clock Networks and PLLs in Arria II Devices
26
December 2010 Altera Corporation
Clock Networks in Arria II Devices
9
2
6
Column I/O clock (5)
Core reference
clock (6)
Row clock (7)
(Note 1)